JPS6028141B2 - Manufacturing method for semiconductor devices - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, selective impurity diffusion and photorin technology have been widely used in the fabrication of semiconductor devices.

However, when forming a diffusion layer using the selective impurity diffusion method, the impurity wraps around and diffuses under the diffusion mask, causing lateral expansion, and when forming a pattern using photorin technology, the dimension increases due to alignment margin, resulting in fine dimensions. This poses a major constraint on the production of semiconductor devices. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel method for manufacturing a semiconductor device that utilizes a technique that enables fine pattern processing and obtains fine dimensions with high precision. In order to meet such objectives, the present invention includes a step of forming a first film containing impurities and mainly containing silicon on a part of the surface of the substrate, and a step of coating the surface of the substrate with the first film. a step of forming a second film containing silicon as a main component, performing a heat treatment to outwardly diffuse impurities contained in the first film into a second film in the vicinity thereof;
forming a region containing the impurity in a part of the second film, thermally oxidizing parts of the first and second films, and electrically connecting at least the first and second films with the thermal oxide film; The method of manufacturing a semiconductor device includes a step of separating the semiconductor device.

Hereinafter, the present invention will be specifically described in detail using preferred embodiments of the present invention.

Embodiment 1 FIGS. 1 to 5 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

The present invention will be explained in detail in the order of steps using the same figure. 1. A polycrystalline silicon film 3'' is formed on a portion of the surfaces of the substrates 1 and 2, which are composed of a silicon wafer 1 and a silicon oxide film 2 provided on its surface (FIG. 1).

In the present invention, various embodiments of the substrate can be employed. For example, as in this embodiment, a silicon wafer 1 on which a bipolar type or field effect type semiconductor element having a PN junction is formed is provided with a silicon oxide film 2, or a semiconductor element having a PN junction is formed on a sapphire substrate. A silicon wafer itself or a silicon wafer on which a semiconductor region is formed and an insulating film is provided on the surface thereof can be used as the substrate. The polycrystalline silicon film 3 has a thickness of about 4000 A by CVD, which is formed at a reaction temperature of about 65 mm using SiH4 and N2-based reaction gases, and is processed into a predetermined pattern shape by photorin technology. It is what was done.

Polycrystalline silicon film 3 before or after pattern processing
is doped with arsenic at a concentration of 5 x 10 atoms/atom (Figure 2).

Phosphorus, boron, etc. can also be used as impurities. The impurity-doped polycrystalline silicon film 3a also serves as an impurity diffusion source in the present invention. 2 CV all over
A polycrystalline silicon film 4 having a thickness of about 2000 Å is formed using the D method or the like (FIG. 3).

3 Heat treatment (e.g. 950q0, 3 in nitrogen atmosphere)
arsenic-doped polycrystalline silicon film 3a.
Arsenic (impurity) is diffused into the polycrystalline silicon film 4 to form a polycrystalline silicon film 4a containing arsenic (FIG. 4).
.

In this case, a thin silicon oxide film is formed on the surface of the polycrystalline silicon film 4 by light oxidation (900 qo, 30 minutes in a dry oxygen atmosphere) on the surface of the polycrystalline silicon film 4, and then heat treatment is performed to remove arsenic. It is also possible to form a polycrystalline silicon film 4a.

This is a mask (inhibition film) for preventing out-diffusion in order to prevent out-diffusion of arsenic from the arsenic-doped polycrystalline silicon film 3a on the surface of the polycrystalline silicon film 4a. ) is performed by providing a silicon oxide film. As described above, the present invention provides impurities (for example, arsenic) in selective regions 4a of polycrystalline silicon film 4.
When diffusing is performed using the arsenic-doped polycrystalline silicon film 3a as the impurity source as a base, and since the arsenic-doped polycrystalline silicon film 3a has a predetermined pattern, a region 4a with a predetermined pattern can be formed. It is.

That is, the dimension L of the region 4a shown in FIG. 4 is determined by the dimension of the arsenic-doped polycrystalline silicon film 3a and the lateral diffusion length d of arsenic, and the dimension d is unique depending on the heat treatment conditions and the type of impurity. By being able to specify , the dimension L can be controlled with high precision by the dimension 1. Therefore, the fine pattern region 4a can be obtained with self-alignment based on the pattern of the arsenic-doped polycrystalline silicon film 3a. 4 Thermal oxidation of polycrystalline silicon films 4 and 4a (75
4a is completely thermally oxidized to form a silicon oxide film 5 (FIG. 5).

At this time, the surface portion of the polycrystalline silicon film 4 is also slightly oxidized to form a thin silicon oxide film 5a. This film thickness difference is due to the property that the polycrystalline silicon film 4a containing impurities has a higher oxidation rate than the polycrystalline silicon film 4 that does not contain impurities, that is, the polycrystalline silicon film due to the difference in impurity concentration. This is based on the use of differences in oxidation rates. Note that the impurity-doped polycrystalline silicon film 3a serves as an impurity-containing region containing impurities.
In the above examples, a material containing arsenic was used, but a material containing phosphorus, a material containing boron, etc. can also be used. Further, instead of the polycrystalline silicon films 3 and 4 in the above embodiments, a polycrystalline silicon film, a semicrystalline silicon film, or the like containing platinum, molybdenum, or the like can be used.

As described above, the method for manufacturing a semiconductor device according to the present invention provides various effects as described below.

'1- In forming the impurity-doped polycrystalline silicon film 4a in a predetermined pattern, the diffusion method is performed by providing an impurity diffusion source, that is, an impurity-containing region such as an arsenic-doped polycrystalline silicon film, under the non-doped polycrystalline silicon film 4. In addition, a silicon oxide film 5 for electrically separating polycrystalline silicon films 3 and 4 is used.
The formation of the polycrystalline silicon film takes advantage of the difference in oxidation rate due to the difference in impurity concentration of the polycrystalline silicon film.

Therefore, the pattern of the arsenic-doped polycrystalline silicon film 4a that is intertwined with the pattern of the arsenic-doped polycrystalline silicon film 3a, which is the impurity-containing region, can be formed in a self-aligned manner.
A thick silicon oxide film 5 pattern matching this arsenic-doped polycrystalline silicon film 4a pattern can be formed with self-alignment. Therefore, in the present invention, since the silicon oxide film 5 for electrically isolating the polycrystalline silicon films 3 and 4 can be formed with self-alignment, the silicon oxide film 5 can be electrically isolated from the polycrystalline silicon films 3 and 4 with fine pattern dimensions. be able to.

This is due to the fact that self-alignment allows microfabrication and fine dimension regulation that can be controlled with high precision.
Therefore, the present invention can produce fine patterns with dimensions that can be controlled with high precision.
Highly integrated circuits and finely structured semiconductor elements can be easily obtained.

'2) The present invention can be applied to the production of various types of semiconductor devices such as multilayer wiring in integrated circuits that require fine patterns, active regions of each semiconductor element, and electrode wiring, and can be applied to the production of various types of semiconductor devices, such as multilayer wiring in integrated circuits that require fine patterns, and the self-alignment process of various devices. This is something that can be achieved. Embodiment 2 FIGS. 6 to 11 show CCDs (charge-coupled devices, Char history CCDs) that are other embodiments of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing method of the device (Device) in the order of steps.

The present invention will be explained in detail in the order of steps using the same figure. The surface of the IP type silicon wafer 6 is thermally oxidized at 1000 DEG C. in a dry oxygen atmosphere for about 12 minutes to form a gate oxide silicon film 7 of about 800 A (FIGS. 6 and 7).

Next, a polycrystalline silicon film of about 3000 A is formed on the surface of the gate oxide silicon film 7 by the CVD method, and phosphorus is thermally diffused into this to form a phosphorus-doped polycrystalline silicon film 8 with a surface concentration of 1×1 atoms. Form.

At this time, a low concentration N-type layer is formed on the surface of the P-type silicon wafer 6 (FIG. 7). 2. The phosphorus-doped polycrystalline silicon film 8 is selectively removed using photorin technology to form a gate electrode 8 pattern made of the phosphorus-doped polycrystalline silicon film as shown in FIG.

Next, boron ions are implanted (100 keV) into the N-type layer 9 through the gate silicon oxide film 7 whose surface is exposed.
, 2 x 1 and 1 atom/s), followed by annealing for 100,030 and 4 minutes to form a N-type layer with a lower concentration than the N-type layer 9.
- forming a mold layer 10 (FIG. 8); 3 2000 on the entire surface
A polycrystalline silicon film 11 having a thickness of approximately A is formed (FIG. 9).

A heat treatment (95 mm, 30 minutes in a nitrogen atmosphere) is performed to diffuse phosphorus outward into the polycrystalline silicon film 11 in the vicinity of the phosphorus-doped polycrystalline silicon film 8, thereby forming a phosphorus-doped polycrystalline silicon film 11a. Figure 10).

4 Low temperature thermal oxidation (750℃, 8 in wet oxygen atmosphere)
time) and the first and second layers of polycrystalline silicon films 8 and 11
The eleventh
figure).

In this case, the second layer phosphorus-doped polycrystalline silicon film 11
Since the oxidation rate of a is higher than that of the doped polycrystalline silicon film 11, the boundary region between the first layer and the second layer can be formed into silicon oxide. That is, the silicon oxide film 12 is formed with dimension 1 shown in FIG. 11 as small as possible.

This dimension 1 is compared to the lateral length of the thermal diffusion of phosphorus from the first-layer IJ-doped polycrystalline silicon film 8 to the second-layer polycrystalline silicon film 11, and is a minute dimension. be. 5 Post-processing is performed using known technology to perform interlayer insulating film, contact photoresist process, and electrode formation.
Get the CD.

Note that when both ends (not shown) of the ninth layer of polycrystalline silicon film 11 are cut at the end of the previous step to perform electrical isolation, the MOS type element having the first layer of polycrystalline silicon film and the second layer of polycrystalline silicon film 11 are separated. A plurality of MOS type elements having crystalline silicon films can be formed. As mentioned above, the CC according to the present invention
The manufacturing method of D is a MOS having a first layer of polycrystalline silicon film.
The type element and the MOS pole element having the second layer polycrystalline silicon film can be provided very close to each other.

This process involves forming a silicon oxide film with dimensions determined by the lateral diffusion length of impurities from the first layer polycrystalline silicon film, and using this silicon oxide film to form the first layer polycrystalline silicon film and the second layer This is due to electrical isolation between the polycrystalline silicon film and the polycrystalline silicon film. Therefore, the element dimensions of the QCCD can be formed with as small an area as possible; (1)
Since there is no need to align the polycrystalline silicon films of the first and second layers, the gap between them can be made extremely short. Since the CCD has characteristics such as being able to be manufactured, the capacitance load is small, and a CCD with extremely low power consumption can be manufactured.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIGS. 6 to 11 show a method for manufacturing a CCD according to another embodiment of the invention in order of steps. FIG. 6...Silicon wafer, 2,7...Silicon oxide film,
3a, 8... Polycrystalline silicon film containing impurities, 4, 11... Polycrystalline silicon film, 5, 5a, 12,
12a...Silicon oxide film, 9...N-type layer, 10...
...N-type layer. Digit '4*z Zuzawa 3 Zusei 4 firewood 5 chrysanthemum G pattern 7 and 8 Zuki? Illustration /o Picture scroll 4

Claims (1)

[Scope of Claims] 1. A step of forming a first film containing impurities and mainly composed of silicon on a part of the surface of the substrate, and applying silicon so as to cover the surface of the substrate with the first film. A process of outwardly diffusing the main component into the second coating and forming the second coating, and a heat treatment to remove the impurities contained in the first coating from the second coating in the vicinity thereof. a step of forming a region containing the impurity in a part; and a step of thermally oxidizing a part of the first and second films and electrically isolating at least the first and second films by the thermal oxide film. A method for manufacturing a semiconductor device comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first and second films are polycrystalline silicon films.