JPH0734441B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0734441B2 JPH0734441B2 JP62220742A JP22074287A JPH0734441B2 JP H0734441 B2 JPH0734441 B2 JP H0734441B2 JP 62220742 A JP62220742 A JP 62220742A JP 22074287 A JP22074287 A JP 22074287A JP H0734441 B2 JPH0734441 B2 JP H0734441B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- wiring
- semiconductor device
- nitrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 24
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims 4
- 239000010936 titanium Substances 0.000 claims description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 21
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 11
- 238000000137 annealing Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
Landscapes
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置において低抵抗で、高温に耐えるチ
タン・シリサイド配線を形成する方法に関するものであ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a titanium / silicide wiring having low resistance and high temperature resistance in a semiconductor device.
従来の技術 超LSI半導体の配線形成では抵抗を下げること、および
高温加熱に耐えるチタン・シリサイドが従来のポリシリ
コンやアルミニウム（Al）に代って広く用いられてい
る。この場合の配線の形成方法を第２図（ａ）〜（ｄ）
の工程順断面図を用いて説明する。2. Description of the Related Art Titanium silicide, which is resistant to heating and high temperature heating, has been widely used in place of conventional polysilicon and aluminum (Al) in forming wiring of VLSI semiconductors. The wiring forming method in this case is shown in FIGS.
This will be described with reference to the process order cross-sectional views.
第２図（ａ）のように、ｐ型Si基板１の表面に、熱酸化
法によりSiO2膜２を形成し、コンタクト窓となる部分の
SiO2膜を開孔し、不純物拡散を行ってSi基板にn+拡散層
６を形成し、次に、MOSトランジスタ素子のゲートを形
成する工程でポリシリコン膜３とチタン（Ti）膜４から
なる二層膜を形成し、通常のフォトリソグラフィー法に
よって、パターニングを行うためのフォトレジストパタ
ーン５を形成する。次いで、第２図（ｂ）のようにフォ
トレジスト５をマスクとして、ドライエッチング法によ
り、Ti膜４とポリシリコン膜３をパターニングを行う。
次に、第２図（ｃ）のようにフォトレジスト膜５を除去
する。そして、さらに、800℃〜900℃の高温でアニール
することにより第２図（ｄ）のようにTiとポリシリコン
との反応により、TiSi2組成の安定したチタン・シリサ
イド膜９が形成される。As shown in FIG. 2 (a), a SiO 2 film 2 is formed on the surface of the p-type Si substrate 1 by a thermal oxidation method to form a contact window.
The SiO 2 film is opened, impurities are diffused to form the n + diffusion layer 6 on the Si substrate, and then the polysilicon film 3 and the titanium (Ti) film 4 are formed in the step of forming the gate of the MOS transistor element. Then, a two-layer film is formed, and a photoresist pattern 5 for patterning is formed by an ordinary photolithography method. Then, as shown in FIG. 2B, the Ti film 4 and the polysilicon film 3 are patterned by a dry etching method using the photoresist 5 as a mask.
Next, the photoresist film 5 is removed as shown in FIG. Then, by annealing at a high temperature of 800 ° C. to 900 ° C., a titanium / silicide film 9 having a stable TiSi 2 composition is formed by the reaction between Ti and polysilicon as shown in FIG. 2 (d).
発明が解決しようとする問題点 超LSIでの配線の最小加工寸法は微細化が要求され、現
在の1MビットDRAMでは、１μｍ程度の寸法が使用されて
いる。また、配線の加工寸法精度は±0.1の高精度が要
求されている。しかるに従来法によるポリサイド配線
（シリサイド膜とポリシリコン膜の二層膜）の形成で
は、第２図（ｂ）に示すように、Ti膜４とポリシリコン
膜３のドライエッチング法で行われている。この場合例
えば、Ti膜0.1μm,ポリシリコン膜0.2μｍを通常のドラ
イエッチング法により行うと0.2〜0.3μｍ程度のサイド
エッチが生じ、配線の寸法変化が大きくなり、かつ配線
幅の変動も大きく、抵抗値の増大や信頼性の保持に不都
合である。Problems to be Solved by the Invention The minimum processing size of wiring in VLSI is required to be miniaturized, and the size of about 1 μm is used in the current 1 Mbit DRAM. In addition, the wiring dimensional accuracy is required to be as high as ± 0.1. However, in forming the polycide wiring (two-layer film of the silicide film and the polysilicon film) by the conventional method, as shown in FIG. 2B, the dry etching method of the Ti film 4 and the polysilicon film 3 is performed. . In this case, for example, when a Ti film of 0.1 μm and a polysilicon film of 0.2 μm are formed by an ordinary dry etching method, side etching of about 0.2 to 0.3 μm occurs, the dimensional change of the wiring becomes large, and the fluctuation of the wiring width is large. It is inconvenient to increase resistance and maintain reliability.
問題点を解決するための手段 本発明の方法は、ポリシリコン膜とTi膜を形成した後、
配線パターンを形成するためのパターニングを行う場
合、従来のドライエッチング法に代って、窒素（Ｎ）イ
オンをイオン注入法により高濃度にTi膜中に選択的に注
入し、アニールを行って注入層にチタン・ナイトライド
（TiN）を、注入外領域にTiシリサイドを、それぞれ形
成し、形成されたTiNをウェットエッチング法によりTiN
のみを選択的に除去することによってTiシリサイド配線
を形成することを特徴としている。Means for Solving the Problems According to the method of the present invention, after forming a polysilicon film and a Ti film,
When patterning to form a wiring pattern, nitrogen (N) ions are selectively implanted into the Ti film at a high concentration by an ion implantation method instead of the conventional dry etching method, and annealing is performed to implant. Titanium nitride (TiN) is formed in the layer and Ti silicide is formed in the non-implanted region, and the formed TiN is formed by wet etching.
It is characterized in that a Ti silicide wiring is formed by selectively removing only this.
作用 この方法を用いることにより配線のパターニング形成寸
法は窒素のイオン注入により形成されるため、注入の遮
蔽マスクに忠実に形成され、寸法の変化量は0.2μｍ以
下に形成でき、抵抗値の変化の少ない微細寸法の配線が
形成される。従来のプラズマによるパターニングに比較
し、イオン注入によりパターニングされるため、マスク
寸法に忠実に形成することができる。By using this method, the wiring patterning formation dimension is formed by ion implantation of nitrogen, so that it is formed faithfully to the implantation mask, and the variation in dimension can be formed to 0.2 μm or less. Wirings with small fine dimensions are formed. Since patterning is performed by ion implantation as compared with conventional patterning by plasma, it is possible to form the pattern faithfully to the mask size.
実施例 本発明の方法の一例を第１図を用いて説明する。第１図
（ａ）のように、ｐ型Si基板１の表面に、熱酸化法によ
りSiO2膜２を形成し、コンタクト窓となる部分のSiO2膜
を開孔し、不純物拡散を行ってSi基板にn+拡散層６を形
成し、次にMOSトランジスタ素子のゲートを形成する工
程でポリシリコン膜３とTi膜４とからなる二層膜を形成
した。ポリシリコン膜３とTi膜の厚さはそれぞれ0.2μ
ｍと0.1μｍである。次に第１図（ｂ）に示すように、
1.5〜２μｍ厚さのフォトレジスト膜５をイオン注入の
遮蔽マスクとして、窒素イオンをエネルギー200KeV〜40
0KeVで注入量５×1017／cm2程度の注入を行う。次いで
フォトレジスト５を除去し、Ar等不活性ガス中で650〜7
00℃で10秒から30秒程度のアニールを行うことにより、
第１図（ｃ）のように、アニール中にＮ注入層にはTi膜
中へのSiの拡散は抑制されTiシリサイドは形成されない
ため、窒素イオン注入層にはTiN8が、未注入層にはTiシ
リサイド層９がそれぞれ形成される。アニールの雰囲気
は、Tiの酸化あるいは窒化を生じさせないように、窒素
以外の不活性ガス、いわゆる非窒素の不活性ガス中で行
うか又は、真空中あるいは1Torr以下の減圧化で行うと
良い。Example An example of the method of the present invention will be described with reference to FIG. As in FIG. 1 (a), the surface of the p-type Si substrate 1 by thermal oxidation to form a SiO 2 film 2, and opening the SiO 2 film in a portion serving as a contact window, and an impurity diffusion An n + diffusion layer 6 was formed on the Si substrate, and then a two-layer film consisting of the polysilicon film 3 and the Ti film 4 was formed in the step of forming the gate of the MOS transistor element. The thickness of polysilicon film 3 and Ti film is 0.2μ each.
m and 0.1 μm. Next, as shown in FIG. 1 (b),
Using the photoresist film 5 having a thickness of 1.5 to 2 μm as a mask for ion implantation, nitrogen ions are used at an energy of 200 KeV to 40
An injection amount of about 5 × 10 17 / cm 2 is performed at 0 KeV. Next, the photoresist 5 is removed, and 650-7 in an inert gas such as Ar.
By annealing at 00 ℃ for 10 to 30 seconds,
As shown in FIG. 1 (c), since diffusion of Si into the Ti film is suppressed in the N-implanted layer during the annealing and Ti silicide is not formed, TiN8 is formed in the nitrogen ion-implanted layer and TiN8 is not formed in the unimplanted layer. Ti silicide layers 9 are formed respectively. The annealing atmosphere is preferably performed in an inert gas other than nitrogen, so-called non-nitrogen inert gas, or in a vacuum or at a reduced pressure of 1 Torr or less so as not to cause oxidation or nitridation of Ti.
アニールはランプアニール法などを用いれば10秒〜30秒
の短時間で行える。次に第１図（ｄ）に示すように、Ti
N層８をウェットエッチング法により除去する。これはH
2O2＋NH4OH＋H2Oの混合液に浸すことにより、TiN層８は
溶解し、Tiシリサイド層９を残すことができる。次いで
Tiシリサイド層の安定化のため、850〜900℃で10秒〜30
秒のアニールを行うと、安定で低抵抗のTiSi2が形成さ
れる。また、残存する注入層の下のポリシリコン膜を通
常のドライエッチング法を用いて除去すると、第１図
（ｅ）のように配線パターンが形成される。Annealing can be performed in a short time of 10 to 30 seconds by using a lamp annealing method or the like. Next, as shown in FIG. 1 (d), Ti
The N layer 8 is removed by the wet etching method. This is H
By soaking in a mixed solution of 2 O 2 + NH 4 OH + H 2 O, the TiN layer 8 is dissolved and the Ti silicide layer 9 can be left. Then
10 seconds to 30 at 850 to 900 ° C to stabilize the Ti silicide layer
When the second annealing is performed, stable and low-resistance TiSi 2 is formed. Further, when the polysilicon film under the remaining injection layer is removed by a normal dry etching method, a wiring pattern is formed as shown in FIG. 1 (e).
発明の効果 この方法により、配線のパターニング寸法は窒素のイオ
ン注入により形成され、配線マスクに対する寸法変化量
は0.2μｍ以下となり、従来のドライエッチング法によ
る0.2〜0.3μｍ程度と比較し、微細で安定したパターニ
ングを行うことができる。又再現性も非常に良好であ
る。EFFECTS OF THE INVENTION According to this method, the patterning dimension of the wiring is formed by ion implantation of nitrogen, and the dimension change amount with respect to the wiring mask is 0.2 μm or less, which is fine and stable as compared with about 0.2 to 0.3 μm by the conventional dry etching method. Patterning can be performed. The reproducibility is also very good.
第１図（ａ）〜（ｅ）は本発明の方法によりチタン・シ
リサイド配線を形成するプロセスを説明するための工程
順断面図、第２図は従来の方法によりチタン・シリサイ
ド配線を形成する方法を示す工程順断面図である。 １……Si基板、２……SiO2膜、３……ポリシリコン膜、
４……Ti膜、５……フォトレジスト膜、６……n+拡散
層、７……窒素注入Ti層、８……チタン・ナイトライド
層、９……チタン・シリサイド層。1 (a) to 1 (e) are sectional views in order of steps for explaining a process of forming a titanium / silicide wiring by the method of the present invention, and FIG. 2 is a method of forming a titanium / silicide wiring by a conventional method. FIG. 1 ... Si substrate, 2 ... SiO 2 film, 3 ... polysilicon film,
4 ... Ti film, 5 ... photoresist film, 6 ... n + diffusion layer, 7 ... nitrogen-implanted Ti layer, 8 ... titanium nitride layer, 9 ... titanium silicide layer.
Claims (3)
薄膜中に選択的に窒素のイオン注入を行い、その後、熱
処理によって前記窒素イオン注入領域以外の領域に選択
的にチタン・シリサイドを同窒素イオン注入領域にチタ
ン・ナイトライドを形成し、その後、前記チタン・ナイ
トライド領域を除去することを特徴とする半導体装置の
製造方法。1. A Ti thin film is formed on the surface of a Si layer, and then the Ti thin film is formed.
Nitrogen is selectively ion-implanted into the thin film, and thereafter, heat treatment is performed to selectively form titanium silicide in a region other than the nitrogen ion-implanted region and titanium nitride in the same nitrogen ion-implanted region. A method for manufacturing a semiconductor device, which comprises removing a titanium nitride region.
ことを特徴とする特許請求の範囲第（１）項記載の半導
体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a non-nitrogen inert gas.
る特許請求の範囲第（１）項記載の半導体装置の製造方
法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in vacuum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62220742A JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62220742A JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6464236A JPS6464236A (en) | 1989-03-10 |
| JPH0734441B2 true JPH0734441B2 (en) | 1995-04-12 |
Family
ID=16755817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62220742A Expired - Lifetime JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0734441B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3588922B2 (en) * | 1996-07-08 | 2004-11-17 | トヨタ自動車株式会社 | Vehicle travel guidance system |
-
1987
- 1987-09-03 JP JP62220742A patent/JPH0734441B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6464236A (en) | 1989-03-10 |
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