JPS6028415B2 - inverter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter circuit using field effect transistors.

Semiconductor circuits, especially semiconductor integrated circuits, are required to have faster operating characteristics.

What is shown in FIG. 6 is a conventionally known inverter circuit that uses two n-channel insulated gate field effect transistors (hereinafter referred to as FETs) for horizontal operation.
dd, Vg and Vss are both power supply voltages, Vin is the input voltage Vout is the output voltage, 12 and ld6 are each FETQ
5. This is the current flowing through Q. When using enhancement type FETs as FETQ5 and Q, usually FETQ
Since the on-resistance of the FET Q5 is several tens of times that of the FET Q5, the delay at the rise of the output voltage is considerably larger than the delay at the fall of the output voltage, making it impossible to meet the above-mentioned demand for high speed. In other words, FIG. 7 shows the output characteristics of the inverter circuit shown in FIG.
are shown to be 3 of Vout, and Vo, respectively, and the output terminal VO when the input voltage Vin of the inverter circuit is given to the input terminal VI a stepped input voltage that changes from Vin, to V~. The charging current lc for the grounded load capacity is lc=ld6-ld5(Vin=Vi
3) [However, ld5 (Vin=Vi ratio) is given by the current ld5 when Vin=Vi ratio], and as the output voltage Vout approaches the Vo peak 3 as shown in FIG.
6 suddenly decreases, the charging current lc also decreases rapidly, which increases the delay when the output voltage Vo peak rises.

This delay phenomenon is caused by depression type FE as FETQ.
When using T, or a NOR circuit formed by connecting other FETs in parallel to FETQ5 or an NA formed by connecting them in series.
A similar problem occurs in the case of an ND circuit, so a constant current source type load in which the charging current lc does not change regardless of changes in the output voltage Vout has been required.

For this purpose, a depletion type claw ET with the gate and source connected is sometimes used as a constant current source type load.
When the output voltage is large, the back gate bias effect makes it difficult for current to flow, and the depletion type F
The current changes due to variations in the threshold voltage of the ET, and variations in the low-level potential of the output voltage and variations in the delay also pose problems, making it impossible to fully meet the above-mentioned demand for higher speeds. something that has been done,
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof, with the aim of providing an inverter circuit that is equipped with a circuit having load resistance and is capable of increasing speed.

As shown in FIG. 1, the inverter circuit according to the present invention uses three enhancement type FETs Q, Q2, Q3, and connects the drain of the first FETQ, the source of the second FETQ2, and the gate of the third FETQ3 Connect and FETQ
, and the source of FETQ3 are connected, and F
The drains of FETQ similar to these are connected to the sources of ETQ, , Q3, and the gate of FETQ4 is connected to the input terminal V.
1. The drain of FETQ (or the source of FETQ., Q3) is used as the output terminal VO. Then FETQ
2 gate and drain, FETQ drain and FET
The source of ETQ4 has power supply voltages V2, V2, V2, V2, V2, and V2, respectively.
dd and Vss are applied. Further, the voltage yct to be applied to the gate of FETQ is a voltage that determines the characteristics of the circuit of the present invention, and is Vdd+VT (VT is the voltage used for the FE used).
T's threshold voltage) is fixed at a certain value. Vin and Vout are the input voltage and output voltage of the inverter circuit, respectively, or ld,, ld2, ld3, and 14.
are the currents flowing through FETQ, Q2, Q3, and Q4, respectively. In the circuit shown in Figure 1, the on-resistance of FETQ2 is F
The intermediate voltage Vx at the intermediate node VX, which is the connection point between the drain of FETQ and the source of FETQ2, should be several tens of times the on-resistance of ETQ, and in order to have inverter characteristics.
shows the characteristics shown in FIG. 2A with respect to the output voltage Vout. In other words, when the output voltage Vout is greater than Vct-VT, FETQ is off, so V
> When Vg90VT, Vx=V adjacent. (Vgg
When 2≦Vg&+VT, Vx=Vg&-VT.
) On the other hand, when the output voltage Vout is smaller than Vct-VT, FETQ is on, so Vx approaches a straight line with a slope of 1 shown in FIG. Therefore, Vout is V
If it is smaller than ct-VT, the currents ld, , ld2 flowing through the FETs Q, , Q2 become as shown in FIG. 3C according to the change in Vx. Also, as shown in Figure 2, Vx-Vou
If the value of t=VT is V, then when Vout is larger than V, the current ld3 flowing through Q becomes as shown in FIG. 3-2 according to the change in Vx. Therefore, the sum of both ld, 10ld
3 is as shown in Fig. 3 E, and FETQ,,Q2,Q
A negative resistance type load is realized. Figure 4 shows FETQ4
Figure 1, which also shows the current lq flowing through the inverter circuit, shows the output characteristics of the inverter circuit. As input voltage Vin, Vin,,V
The output voltage Vout when in3 is applied is Vou
Then, Vou et al. Also, as the input voltage Vin, Vin
The output voltage Vout when 2 is applied is the curve of the current ld4 (Vin=Vin2) in this case and the third
Intersection points A and B with the curves of currents ld and 1d3 shown in the figure,
There are three solutions, V^, VB, and Vc, corresponding to each of C, but only A and C are stable points, and when the input voltage Vin changes from Vin to the Vi ratio, Vout=VA,
When changing from the Vi ratio to Vin2, the solution is Vout:Vc. Here, when Vin=Vin, the steady current of the inverter is the same as in the case of FIG. 7 for comparison. Now, the input voltage V of the inverter circuit shown in FIG.
When a stepped input voltage that changes from Vin to Vin3 is given as in, the charging current for the grounded load capacity of the output terminal VO is lc=ld, 1d3-1d4 (V
in=Vin3) [However, ld4 (Vin=Vi ratio) is V
The current ld4 when in=Vi~ is given by the seventh
As is clear from the comparison with the figure, the output voltage Vout is Vo
Since a large charging current can be obtained until the voltage approaches ut3, the delay when the output voltage Vout rises becomes small.

Note that the time to charge the grounded capacitance of the intermediate node VX with ld, (ld2) is the same as the grounded load capacitance of the output terminal VO with ld, 10 l.
It is appropriate to design the battery so that the charging time is sufficiently long compared to the charging time of d3. As described in detail above, since the inverter circuit of the present invention is equipped with a negative resistance load, the delay in the rise of its output voltage is reduced, making it possible to increase the speed of semiconductor circuits or semiconductor integrated circuits.

Further, the inverter circuit of the present invention has a transfer characteristic exhibiting a hysteresis characteristic as shown in FIG. As is clear from this transfer characteristic, the inverter circuit {1} has a large high-level noise margin and a large low-level noise margin, functions as a noise filter; '2- has an infinite gain; and {3} exhibits hysteresis characteristics. By connecting the output, it has the effect of operating as a flip-flop.

It goes without saying that the above-mentioned effects can be similarly obtained when the circuit of the present invention is used in the configuration of logic circuits such as NAND circuits and NOR circuits. In the above description, an n-type channel insulated gate FET has been referred to, but the circuit of the present invention can be similarly constructed for a p-type channel insulated gate FET, a junction FET, or a Schottky barrier FET.

In addition, V2, which is applied to the gate and drain of FETQ2, the drain of FETQ3, and the gate of FETQ,
V, Vdd, and Vct are not limited to fixed voltages as mentioned above, but may also be control voltages that change over time. For example, it is also possible to add a periodic signal such as a clock as Vg&, Vct. be.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention; FIG. 1 is a circuit diagram of the inverter circuit of the present invention, FIG. 2 is a Vout-Vx characteristic diagram of the inverter circuit, and FIGS. 3 and 4 are diagrams of the inverter circuit of the present invention. 5 is a transfer characteristic diagram of the inverter circuit, FIG. 6 is a circuit diagram of a conventionally known inverter circuit, and FIG. 7 is an output characteristic diagram of the inverter circuit shown in FIG. 6. . Q,,Q2,Q3,Q4...FET,V1...
Input terminal, V○...Output terminal, VX...Intermediate node. Tsutomu' figure Kayotsu figure Kiyoshi 4 figure Hair Ta figure Hair 6 figure Hair J■ Grandchild figure 7

Claims (1)

[Claims] 1 The drain of the first FET, the source of the second FET, and the gate of the third FET are connected, and the first
The source of the FET, the source of the third FET, and the drain of the fourth FET are connected, and the gate of the first FET, the gate and drain of the second FET, and the third FET are connected to each other.
A fixed voltage is applied to the drain of T and the source of the fourth FET, so that the on-resistance of the second FET is equal to that of the first FET.
T, and the fixed voltage applied to the gate of the first FET is set to a value smaller than the sum of its threshold voltage and the fixed voltage applied to the drain of the third FET. 2. The circuit part consisting of the third FET is made to have negative resistance, and the fourth FET
An inverter circuit characterized in that the gate and drain of T are used as an input terminal and an output terminal, respectively.