JPS6029134B2 - Storage device control method - Google Patents

Description

[Detailed description of the invention] The present invention relates to general storage control.

Depending on the method, for a storage unit that exceeds the maximum storage capacity limited by the system, a bank switching method is used in which the required storage capacity is set and addressing is performed above or below the maximum storage capacity.
Alternatively, it has been usual to use a virtual storage method in which a storage part exceeding the maximum storage capacity is provided outside the main storage part, and the frequently used external storage part is read into a part of the main memory.

However, the former bank switching method has the drawback that addressing cannot be made the same, and the latter virtual storage method has the drawback that control is difficult.

Therefore, it is an object of the present invention to provide a storage device control method that provides the same addressing and is easy to control.

According to the present invention, there is provided a control method that makes it possible to negotiate a large amount of data by providing an auxiliary memory section to a main memory device having a main memory section and an address section for specifying the address of the main memory section. A predetermined number of addresses of a part of the main memory section constitute an auxiliary memory address section that generates an output for addressing the auxiliary memory section in response to the designation of the address section; A number of consecutive addresses are divided into a plurality of subdivisions so that each subdivision corresponds to one of the predetermined number of addresses, and the addresses of the address part for the auxiliary storage address part are By repeatedly specifying the same address, the address specification is controlled to be moved one by one from the smallest address in the subdivision specified by the output of the auxiliary memory address section to larger addresses one by one, and then By changing the designation to another address, a storage device control method is obtained in which data is read from the final address of the one small section.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention in blocks. In this embodiment, storage unit address information from the central control unit CPU is entered into the address unit ADR of the main storage unit MMU through address buses ABO-15.
At this time, even if the address data is maximum, address bus AB1
If the storage capacity that can be controlled by 6 wires is specified to be within 64k (k stands for kilo, 1 pi, the same applies hereinafter), the data in the storage section MM specified by the address data will be transferred to the data bus DB.
sent to. However, when the address data exceeds 64k, there is no other option but to increase the number of address buses AB to 16 or more.

However, in reality, it is not possible to make the number 16 straight. Therefore, in the method of the present invention, an auxiliary storage unit SUBM for more than 64k is provided, and a main storage unit MM
A part of the main memory section MM in U is set as an auxiliary memory address section SMAD that addresses the auxiliary memory section SUBM, and the auxiliary memory section is divided into several 4 sections, each section being a number of consecutive addresses. It consists of the address of
The 4th section corresponds to each address of the auxiliary memory address section SMAD. Similarly to the main memory section MM, the auxiliary memory address section SMAD is controlled by the central control section CPU.
The address section ADR receives an address designation based on a designation signal sent from the address bus AB via the address bus AB. In such a configuration, negotiation of the auxiliary storage section is performed as follows. Here, to make the explanation easier to understand, the auxiliary memory unit SUBM and the auxiliary memory address unit SMA are
The configuration of D and the relationship between the two will be explained in some detail using tentative numerical values. The original main memory area is now 10 areas, of which 9G areas (0 to 89) are the actual main memory area MM, and the remaining 1 area (90 to 99) is the auxiliary memory address area SMAD. shall be. On the other hand, the auxiliary memory section uses the one at address 50, which is stored as 100-104, 105-109,...
, 145 to 149.
The subdivision addresses 100 to 104 are auxiliary memory address 6M.
10 of the second parcel corresponding to the first address 90 of AD.
The 5th to 10th parcels are made to correspond to the second SMAD address 91, and in the same manner, the 1st parcels are made to correspond to the 90th to 9th addresses in sequence. As can be seen from the above explanation, one address of the auxiliary memory address section SMAD contains five consecutive addresses of the auxiliary memory section, so
As it stands, it is impossible to distinguish between these five. Therefore, to make this distinction, we used a method of repeating the address specification several times. That is, when specifying the 10th group address, for example, the auxiliary memory address control unit SMADC specifies 9 captured areas of the auxiliary memory address SMAD four times in a row, sequentially counts up from 10 gono to 103 flea, and then When changing the designation to another address, for example, address 91, the data in the auxiliary storage unit SUBM is read out at the final address 103 counted up immediately before the change. FIG. 2 is a block diagram showing in detail an example of the configuration of the auxiliary storage address control unit SMADC that performs the above address control together with some other circuits.

The output of the auxiliary memory address section SMAD specified by the address section ADR is accumulated in the main counter section MC from the central control section CPU via the address bus AB (see FIG. 1 above). At this time, the comparison unit COM compares whether the output of this auxiliary memory address unit SMAD is the same or different from the output sent immediately before, and the output of the auxiliary memory address unit SMAD is compared.
The auxiliary counter unit SUBC is the lower bit of the address of
control. That is, if both outputs are the same, the contents of the auxiliary counter SUBC will be further counted up by 11,
The input from the auxiliary memory address section is again input as is to the main counter section. However, when the two outputs are different, new data is input to the main counter section MC, and the contents of the auxiliary counter section SUBC are cleared and returned to zero, but immediately before that, the data of the main counter section MC that had been input and The final data of the auxiliary counter unit SUBC that has been counted up, that is, the final data as a whole, is transferred to the auxiliary memory SU via the auxiliary memory address bus SAB.
The specified auxiliary storage S is sent as the BM address.
The output of the UBM is sent as data to the data bus DB. Note that when the designation to the auxiliary storage address section is not repeated at all, for example, when address 100 was designated in the previous example, the auxiliary counter SUBC is not counted up and remains at zero and moves on to the next designation. In the above embodiment, the auxiliary memory address control unit SMADC is arranged to be included in a part of the main memory unit MMU, but it may be arranged in the auxiliary memory unit SUBM.

Further, as can be seen from the above description, the number of bits of the auxiliary memory address control agent SMADC and the number of output bits of the auxiliary memory unit SUBM are not particularly limited. As can be seen from the above description, according to the present invention, although the auxiliary storage section, which is formally limited and is larger than the main storage section, can be controlled in the same way as the main storage section. It can be controlled in various ways. Furthermore, according to the present invention, even if the storage capacity is suddenly increased, it is possible to easily control the system by increasing only the hardware without making a large-scale change to the entire system. That is, in the present invention, the non-identical addressing seen in conventional devices is not recognized, nor is the difficulty in control recognized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing an embodiment of the present invention, and FIG. 2 is a detailed diagram showing the configuration of a part of the device shown in FIG. Explanation of symbols: In Figure 1, ADR is the address part, C
PU is the central processing unit, MM is the main memory, MMU is the main memory, SMAD is the auxiliary memory address section, SMADC is the auxiliary memory address control section, and SUBM is the auxiliary memory. MC and SUBC represent a main counter section, and an auxiliary counter section, respectively. Cumulative 1 image 2 images

Claims (1)

[Claims] 1 A control system that enables reading of a large amount of data by adding an auxiliary memory to a main memory having a main memory and an address section for specifying the address of the main memory, A predetermined number of addresses of a part of the section constitute an auxiliary memory address section that receives the designation of the address section and generates an output for specifying the address of the auxiliary memory section; A number of addresses are divided into a plurality of small sections so that each small section corresponds to one of the predetermined number of addresses, and the addresses of the address section and the auxiliary storage address section are specified in the same manner. By repeating this process for the address, the address designation is controlled to be sequentially moved one by one from the smallest address in the small section specified by the output of the auxiliary memory address section to the larger address, and then A storage device control method in which data is read from the final address of the one small partition by changing the designation to another address.