JPS6029255B2 - logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an insulated gate field effect transistor (insulated gate field effect transistor).
Regarding the improvement of the IGFET (commonly referred to as IGFET), in particular, a logic circuit with multiple functions is configured with a smaller number of elements than in the past, thereby reducing power consumption and cost.

[Technical background and problems of the invention]

Figure 1 is a logic circuit diagram that performs a conventional AND-NOR gate operation, and the logic circuit has logic inputs A, B, C, and D.
For this, an output of S:A・B+C・D is obtained.

For this purpose, P-channel type 10FETP P, ~P4 and N
Total of 8 IGFEs of channel type OPETN, ~N4
A complicated circuit configuration using T is required. In other words, this circuit can only have a single logic function with eight FETs, and in order to achieve multi-functionality, it requires more FETs.
must be additionally connected. In addition, considering multi-functionality, there is a conventional logic circuit with 4 inputs and 3 outputs as shown in Figure 2, but in this case, 3 NAND gate circuits are used.
Each gate circuit requires 4 IGFETs, totaling 1
Two IGFETs will be used. In this way, in a subordinate logic circuit, it is difficult to achieve many functions at the same time.
This increases the number of ETs, which not only increases the area occupied by the IC, but also inevitably lowers the yield and increases the price.
Furthermore, the inherent leakage current of FETs varies depending on the manufacturing method, but is generally on the order of several PA to several mA, and an increase in power consumption is unavoidable as the number of elements increases. Also from this point of view, the logic circuits shown in FIGS. 1 and 2 are not suitable for multifunctionalization. [Object of the invention] The present invention was completed based on the above background,
The present invention provides a novel logic circuit that eliminates the above-mentioned drawbacks of the conventional logic circuit, and in particular, the number of constituent elements is significantly reduced compared to the conventional one, and moreover, it is designed to have multiple functions.

[Summary of the invention]

In order to achieve the above object, the logic circuit of the present invention has the following features:
A first channel type IFET and a second channel type first IFET are connected in series, a first logic signal is applied to the gates of these FETs, a source of the first IFET is connected to a first power supply terminal, and the first IFET is connected in series. A first logic circuit section configured to apply a second input to the source of an ET, a first channel type ET and a second channel type ET are connected in series, and the gates of these FETs are connected in series. a second logic circuit section configured by applying a third logic signal to the ET source, applying a fourth logic signal to the ET source, and connecting the source of the Otoshimisaki ET to a second power supply terminal; Channel-shaped first mark ET and second
Channel-shaped first feed ETs are connected in series, the gates of these FETs are connected to the drain output terminal of the first or second logic circuit, and the source of the first ET is connected to the first power supply terminal or the first logic circuit section. a third logic circuit section connected to the drain output terminal and configured by connecting the source of the first bait ET to the drain output terminal or the second power supply terminal of the second logic circuit section; and the first to third logic circuits. the first to third output terminals respectively connected to the respective drain output terminals of the logic circuit section; and diodes coupled to the respective output terminals of the first to third logic circuit sections to assist the logic operation. It is characterized by the fact that

[Embodiments of the invention]

Next, one embodiment of the present invention will be described with reference to FIG. 3a.

The first logic circuit section 1 connects a P-channel type IGFET, P, and an N-channel type IGFET, N, in series, applies a logic input signal A in common to each gate of these FETs,
Connect the source of the FET, P, and the substrate to one power terminal a.
and is configured to provide a logic input signal B to the source and substrate of FET,N.

The output terminal c of this first logic circuit section 1 is connected to the FET, P,
connected to the connection point between the drain of and the drain of S,
,=A+B is obtained. In addition, the above IGFET,
There is a diode D, connected in the direction shown, between the drain of the substrate of IGFET, P, and a diode D, connected in the direction shown, between the drain of IGFET, N, and the substrate.
2 exists. The second logic circuit section 0 is a P-channel type IG
FET, P2 and N-channel type IGFET, N2 are connected in series, a logic input signal c is commonly applied to each gate of these FETs, and the source of the FET, P2 is connected to the substrate to receive a logic input signal here. Give ○, revised FET, N2
Connect the source and board to the other power supply terminal b (ground here)
It is configured by connecting to. The output terminal d of this second logic circuit section 0 is connected to the connection point between the drain of the FET P2 and the drain of N2, and obtains a logic output of S2=CD. Furthermore, there is a diode D3 connected in the direction shown in the figure between the substrate and drain of the IGFET P2,
Similarly, a diode D4 exists between the substrate and drain of FET N2. The third logic circuit section m is a P-channel type IGFET, P3, and an N-channel type IGFET, N
3 are connected in series, and the output signal of the first logic circuit section 1 is commonly applied to each gate of these FETs.
Connect the source and board of No. 3 to power supply terminal a, and connect the IGFET
, N3 are connected to the substrate, and the output signal of the second logic circuit section 0 is applied thereto. The output terminal e of this third logic circuit section m is connected to the connection point between the drain of the superconductor FET P3 and the drain of N3, and S3=A
A logical output of B+CD is obtained. Furthermore, a diode D5 connected in the direction shown is present between the substrate and drain of FET P3, and a diode DB is similarly present between the substrate and drain of FET N3. Next, FIG. 4a shows an example in which the logic circuit of FIG. 3a is incorporated into an integrated circuit device. This shows a so-called SOS type IC in which a semiconductor layer is formed by heteroepitaxially growing silicon, for example, on an insulating substrate 1 made of a spinel type insulator such as sapphire or ruby, and then photoetching it. Here, P channel type FET, P,, P2, P3, N channel type F
ET, N, , N2, N3, power supply terminals a, b, logic input signals A, B, C, D, logic output signals S, , S2, S3 and diodes D, -D6 are all shown in Figure 3a. corresponds to the symbol given. In addition, 2 in the figure is an insulating layer, and each FET, P,
,~P3,. It also serves as a gate insulating film for N, to N3.
3 is a conductive layer used for the wiring layer and each FET gate (electrode).

In the figure, FETs P, ~P3 are all made of semiconductor layers arranged laterally as PNP, and the N-type layer is in a positional relationship corresponding to the gate above and below, as shown in Figure 3a. This corresponds to the board that was installed. Also, in Fig. 4a, FET, N, ~
Both of N3 are formed of semiconductor layers arranged laterally as NPN, of which the P-type layer is vertically opposed to the gate thereof, and corresponds to the substrate described in FIG. 3a. Therefore, if the N layer as a substrate of FET, P, in Fig. 4a is connected to the P layer (source) on the left side as shown by the solid line, this N layer of the substrate and the P layer (drain) on the right side.
A parasitic diode D is formed due to the PN junction between the two.

Similarly, for FETs N, , P2, N2, P3, and N3, parasitic diodes D2, D3, . . .
6 is formed. Next, the operation of the circuit shown in FIG.

Table - When IA=0, B=0, FET, P, is ON, FE
T, N, are turned off, and S. =1 output is obtained.

When A=0 and B=1, although the FET, N, is turned off, the diode D2 is biased in the forward direction, and S, 1 is also output through the FET, P, which is in circle with this D2. When A=1 and B=0, P, is OFF and N, is ON, and S,=0 is output, and when A=1 and B=1, P, is O.
It becomes an FF, and regardless of whether N, is ON or OFF, D2 becomes a forward bias and assists the logic operation, so that S,=1.
Therefore, S. A logical output of =A+B can be obtained.
Next, when C=0 and D=0, FET and N2 are OFF,
Diode D regardless of whether FET and P2 are ON or OFF.
3 is forward biased to assist the logic operation and the output S2 is pulled to the level of D, resulting in an output of S2=0.

When C=0 and D=0, P2 is ON, N2 is FF, and D3
, D4 are reverse biased, resulting in the output of S2=1. C=
1. When ○=0, P2 is OFF, N2 is ON,
The output is S2=0. Also, when C=1 and D=1,
P2 is OFF and N2 is ON, resulting in S2:0. That is, a logical output of S2=C.D can be obtained. Furthermore, since the above results have been obtained, let's consider the third logic circuit section m whose inputs are S, , S2.

When S,=0 and S2=0, FET, P3 is ON, and N3 is O.
It becomes an FF and obtains an output of S3=1. S,=0,S2
When =1, P3 is turned on and N3 is turned off, while diode D6 is biased in the hitting direction, and an output of S3=1 is obtained through P3 and D6. For S,=1, S2;0, P3
is turned off, N3 is turned on, and S3=0. Also S
, = 1, and S2 = 1, P3 is OFF and N3 is ON.
, OFF, the diode D6 is forward biased, assists the logic operation, and can obtain an output of S3=1. That is, S3=S, 10S2=A1B+C・D=
It becomes a logical output of A, B + C, D. Next, FIG. 3b shows another embodiment, and parts similar to those in FIG. 3a are given the same symbols and the explanation thereof will be omitted. Therefore, to explain the different parts from FIG. a, and a diode D7 in the direction shown is additionally connected between the source and drain of P2. In this case, as in the example of Fig. 3a, three types of logical outputs S, = A + B, S2 = CD and S3 = AB + C
D is obtained. Further, since an example in which the circuit of FIG. 3b is incorporated into an integrated circuit device is shown in FIG. 4b, this point will be explained.

In this case as well, since the same symbols are shown in the parts corresponding to the circuit elements shown in FIG. 3b, the structure should be easily understood. To give a slightly supplementary explanation, here, a P channel type IGFET, a P. ~P
3 and a P-type P-wel formed in the base 1.
The difference from FIGS. 3a and 4a is that N-channel type IGFETs, N, .about.N3 are formed in FIG. The substrate 1 corresponds to the substrate of the IGFETs P and .about.P3 in FIG. 3b, and the P-well corresponds to the substrate of the IGFETs N and .about.N3. Note that 2 is an insulating layer, and 3 is a conductive layer such as wiring. Next, Figure 3c
shows still another embodiment of the present invention, in which a diode D8 for auxiliary operation is interposed between the source and drain of the FET, N, in the direction shown in the first logic circuit section 1.
The feature is that a diode D2 is interposed between the grounded substrate of N and the drain of N. The second logic circuit section 0' is characterized by the removal of the diode D3 in FIG. 3b, and the third logic circuit section 0' is characterized by the removal of the diode D3 in FIG. D9 is provided, and the diode D6 is connected between the grounded substrate of N3 and the drain. The logical outputs S, , S2, and S3 are all shown in Figure 3a.
and b. Furthermore, the logic circuits shown in FIGS. 3a to 3c can be represented as a logic block diagram as shown in FIG. 3d. Furthermore, FIG. 5a shows still another embodiment, in which, instead of the example of FIG. 3a, a third logic circuit section is provided between the output of the first logic circuit section 1 and the ground, and its input is received from the output of the second logic circuit section D,
The S3 output is inverted from the case shown in FIG. 3a, and becomes a logical output of AB+CD.

This FIG. 5a can be represented as a logical block diagram as shown in FIG. 5b. Figure 5c is a logic block diagram showing what would happen if a conventional technology were used to construct a multifunctional logic like that shown in Figure 5a, and compared with Figure 5b, It is clear that the number of circuit elements increases and the complexity increases. Furthermore, FIG. 6 shows another embodiment of the present invention, in which the first logic circuit section 1, second logic circuit section 1, and The three logic bond circuit section m has a similar configuration.

However, in the example shown in FIG. 6, an inverter ln receiving input B and an inverter ln2 receiving input c are added, resulting in five logical outputs S, =A・B, S2=C・D, S3=A
・B+C・D, S4:B, Mi=C is obtained. [Effects of the Invention] As described above, in the logic circuit of the present invention, the logic circuit section is configured using two pairs of complementary IGFETs, and by providing a diode to assist the logic operation of the logic circuit section. , can perform reliable logical functions.

Moreover, as mentioned above, the small number of FETs uses at least three logic circuit sections configured with two FETs as units.
Regardless of the configuration, a multifunctional logic with, for example, 4 inputs and 3 outputs can be obtained. Specifically, in the conventional example shown in FIG. 1, only one logic output can be obtained with eight FETs, but in the present invention, three logic outputs can be obtained with six FETs. It will be done. Furthermore, the conventional example shown in FIG. 2 is an extension of the technique shown in FIG. 1, and in order to obtain three logical outputs, the number of elements consisting of 12 FETs is required, which is twice the number of elements of the present invention. . In addition, in the present invention,
When the integrated circuit device shown in Figure 4a is applied, the diode that assists logical operation can be used to arbitrarily create an IGFET source, substrate information N junction, drain/substrate PN junction, etc. depending on the circuit connection method. Therefore, no area is required for each diode.

Further, when the integrated circuit device shown in FIG. 4B is applied, the auxiliary diode D7 must be made by diffusion in addition to the IGFET, but its area is significantly smaller than that of the IGFET. Therefore, the use of diodes in the circuit of the present invention has little effect on the area of the integrated circuit device and can be ignored in terms of the number of elements.

In addition, due to this, the improvement of the degree of integration, improvement of walking speed,
Lower power consumption can be achieved.

[Brief explanation of drawings]

FIG. 1 is a conventional logic circuit diagram, FIG. 2 is a logic block diagram showing a further conventional example, FIGS. 3 a to c are logic circuit diagrams showing an embodiment of the present invention, and FIG. A to c are logic block diagrams showing logic signals, FIGS. 4a and b are cross-sectional views of the circuits shown in FIGS. 3a and b, respectively, constructed by integrated circuit devices, and FIG. 5a is a diagram illustrating the present invention. A logic circuit diagram showing another embodiment of
FIG. 5b is a logical block diagram showing FIG. 5a with logical symbols;
FIG. 5c is a logic block diagram in which a conventional technique is applied to provide the same function as the circuit in FIG. 5a, and FIG. 6 is a logic block diagram showing another embodiment of the present invention. This is a diagram. 1...First logic circuit section, D...
Second logic circuit section, m...Third logic circuit section, A~
D......Logic input signal, S, ~S~...Logic output signal, P, ~P3...P channel type ICF
E.T., N. ~N3...N-channel IGFE
T, D, ~○9...Diode, a...
- First power terminal (VoD), b... Second power terminal (GND). The younger brother 'Zu Ta 2 Zu Shu 3 Zu' is) Figure 3 (b) Mai 3 Zu (C) Shu 3 Zu'〆1 Figure 4 (Ku 1 Ta 4 Figure (BL Ta 7 figure similar) Deta Figure ( b) Tsutomote diagram (C) Figure 6

Claims (1)

[Claims] 1. A first FET of the first channel type and a second FET of the second channel type are connected in series, a first logic signal is applied to the gates of these FETs, and the source of the first FET is connected to the first FET.
A first logic circuit section connected to a power supply terminal and configured to apply a second logic signal to the source of the second FET, a third FET of the first channel type and a fourth FET of the second channel type are connected in series. , a second logic circuit section configured by applying a third logic signal to the gates of these FETs, applying a fourth logic signal to the source of the third FET, and connecting the source of the fourth FET to a second power supply terminal; , a first channel type fifth FET and a second channel type sixth FET are connected in series, the gates of these FETs are connected to the drain output terminal of the first logic circuit section, and the source of the fifth FET is connected to the first power supply terminal. and a third logic circuit section configured by connecting the source of the sixth FET to the drain output terminal of the second logic circuit section. 2 A first channel type first FET and a second channel type second FET are connected in series, a first logic signal is applied to the gates of these FETs, and the source of the first FET is connected to the first FET.
A first logic circuit section connected to a power supply terminal and configured to apply a second logic signal to the source of the second FET, a third FET of the first channel type and a fourth FET of the second channel type are connected in series. , a second logic circuit section configured by applying a third logic signal to the gates of these FETs, applying a fourth logic signal to the source of the third FET, and connecting the source of the fourth FET to a second power supply terminal; , a first channel type fifth FET and a second channel type sixth FET are connected in series, the gates of these FETs are connected to the drain output terminal of the second logic circuit section, and the source of the fifth FET is connected to the first power supply terminal. and a third logic circuit section configured by connecting the source of the sixth FET to the drain output terminal of the first logic circuit section.