JPH073948B2 - Multi-input-multi-output logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and sometimes to a multi-input / multi-output logic circuit.

[Conventional technology]

Conventionally, this kind of logic circuit uses a plurality of logic circuits when different logic outputs are made using the same input.

FIG. 6 is a connection diagram showing an example of a conventional logic circuit. A logic circuit having an output O ₁ of AND-NOR logic of input signals A, B and C and an output O ₂ of NAND logic of A, B is shown in FIG. Show. That is, the logic circuits are individually configured for the outputs O ₁ and O ₂ .

[Problems to be Solved by the Invention]

The above-described conventional logic circuit has a drawback in that when the same input is used and different logic outputs are performed, a circuit for outputting the logic is individually required.

It is an object of the present invention to provide a multi-input / multi-output logic circuit which solves the above drawbacks by utilizing commonly-usable elements.

[Means for Solving the Problems]

The multi-input / multi-output logic circuit of the present invention has first and second vertically stacked transistors that gate-input first and second signals and source-input a first power supply, and gate-input third signals. A third transistor that inputs the first power source as a source and shares a drain with the first vertically stacked transistor, and a gate input for the third signal and a source input for a drain output of the third transistor, A fourth transistor that shares a drain with two vertically stacked transistors; a fifth transistor that receives a gate of the first signal and a source of a second power source; and a fifth transistor that shares a drain with the fourth transistor; A second transistor is provided as a gate, the second power source is provided as a source, and the sixth transistor shares a drain with the fourth transistor, and the first and second transistors are provided. Loading transistor and the third transistor has a same transistor characteristics, the fourth,
The fifth and sixth transistors have the same transistor characteristics and have a complementary relationship with the transistor characteristics of the third transistor, and the drain of the third transistor is used as the first output signal for the fourth transistor. It is configured so that the drain of the transistor serves as the second output signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The logic circuit shown in the figure has an output O ₁ of AND-NOR logic of input signals A, B and C and an output O ₂ of NAND logic of A, B, and the truth value list is shown in FIG.

When C = 0, the p-transistor 3 is turned on and the n-transistor 4 is turned off. At this time, if A = B = 0, the p-transistors 1 and 2 are turned on and the n-transistors 5 to 8 are turned off.
The output O ₁ is “1” through the transistors 1 to 3, and the output O ₂ is “1” through the transistors 1 and 2.

When C = 0, if A = 0 and B = 1, p-transistor 2 and n-transistors 5 and 7 are ON, p-transistor 1 and n-
Transistors 6 and 8 are OFF, output O ₁ is transistor 2
The output O ₂ becomes “1” through the transistor 2 through 3 to 3.

When C = 0 and A = 1 and B = 0, p-transistor 1 and n-transistors 6 and 8 are ON, p-transistor 2 and n-
Transistors 5 and 7 are off, and output O ₁ is transistor 1 and
Through "3", the output O ₂ becomes "1" through the transistor 1.

When C = 0 and A = 1 and B = 1, n-transistors 5 to 8
Is ON, p-transistors 1 and 2 are OFF, output O ₁ is “0” through transistors 5 and 6, output O ₂ is transistors 7 and 8.
Becomes "0" through.

Next, when C = 1, the p-transistor 3 is in the OFF state and the n-transistor 4 is in the ON state, the output O ₁ is always "0" regardless of the values of A and B, and the output O ₂ is C = 0. Same as time. Therefore, O ₁ becomes the AND-NOR output of A, B and C, and O ₂ becomes the NAND output of A, B.

FIG. 3 is a logical value list in which the input C is replaced with the NOR logic outputs of A and B in the above embodiment. At this time, output O ₁ is Su
Since the output O ₂ becomes Carry in m, it is equal to the Half Adder circuit. Therefore, the present invention is particularly effective when used as a basic element of an arithmetic circuit.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. The logic circuit shown in the figure has an OR-NAND logic output O ₃ of the input signals A, B and C and a NOR logic output O ₄ of A, B, and the truth value list is shown in FIG.

When C = 1, the p-transistor 19 is in the OFF state and the n-transistor 24 is in the ON state. If A = B = 0 at this time, p-transistor 19 is in the p-transistor.
Transistors 20-23 are ON, n-Transistors 25-26 are OFF
And output O ₃ is "1", output through transistors 20 and 22
O ₄ becomes “1” through the transistors 21 and 23.

If C = 1 and A = 0 and B = 1, p-transistors 20 to 21
The n-transistor 25 is turned on, the p-transistors 22 to 23 and the n-transistor 26 are turned off, the output O ₃ is "0" through the transistors 25 and 24, and the output O ₄ is "0" through the transistor 25.

If C = 1 and A = 1 and B = 0, p-transistors 22 to 23
The n-transistor 26 is turned on, the p-transistors 20 to 21 and the n-transistor 25 are turned off, the output O ₃ is "0" through the transistors 26 and 24, and the output O ₄ is "0" through the transistor 26.

If C = 1 and A = 1 and B = 1, p-transistors 20-23
Is OFF, the n-transistors 25 to 26 are ON, the output O ₃ is “0” through the transistors 25, 26 and 24, and the output O ₄ is “0” through the transistors 25 and 26.

Next, when C = 0, the n-transistor 24 is in the OFF state and the p-transistor 19 is in the ON state, the output O ₃ is always "1" regardless of the values of A and B, and the output O ₄ is C = 1. Same as time. Therefore, O ₃ is the OR-NAND output of A, B and C, and O ₄ is the NOR output of A, B.

〔The invention's effect〕

As described above in detail, the multi-input / multi-output logic circuit of the present invention receives the first and second signals by gate input and outputs the first and second signals.
First and second vertically stacked transistors for source-inputting the power source, and a third transistor sharing a drain with the first vertically-stacked transistor for gate-inputting the third signal and source-inputting the first power source And a gate input of the third signal, a source input of the drain output of the third transistor, and a fourth transistor sharing a drain with the second vertically stacked transistor, and a gate input of the first signal. A fifth transistor, which receives a second power source as a source and shares a drain with the fourth transistor, and a fifth signal, which receives a gate input of the second signal and inputs the second power source as a source, connects the fourth transistor and the drain to each other. A sixth transistor in common, wherein the first and second vertically stacked transistors and the third transistor have the same transistor characteristics. The fourth, the third with transistor fifth, and sixth comprises the same transistor characteristics
Since it has a complementary relationship with the transistor characteristics of the transistor of No. 3, and the drain of the third transistor is used as the first output signal and the drain of the fourth transistor is used as the second output signal, The advantage is that a plurality of different logic outputs can be provided with a smaller number of elements.

[Brief description of drawings]

1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is an explanatory diagram showing a truth value list thereof, FIG. 3 is an explanatory diagram showing a truth value list when an input is changed, and FIG. FIG. 5 is a circuit diagram showing a second embodiment, FIG. 5 is an explanatory diagram showing a truth value list thereof,
FIG. 6 is a circuit diagram showing a conventional example. 1-3 ... p-MOS transistors, 4-8 ... n-MOS transistors.

Claims (1)

[Claims] 1. A gate input for first and second signals
Of the first and second vertically stacked transistors which source-inputs the power source, and a third transistor which inputs the third signal to the gate and inputs the first power source as the source and shares the drain with the first vertically stacked transistor. A gate input of the third signal, a source input of a drain output of the third transistor and a drain sharing a drain with the second vertically stacked transistor; and a gate input of the first signal. A fifth transistor that inputs a second power source as a source and shares a drain with the fourth transistor, and a fifth transistor that inputs a gate to the second signal and inputs the second power source to input the fourth transistor and a drain. A shared sixth transistor, wherein the first and second vertically stacked transistors and the third transistor have the same transistor characteristics. , The above
The fourth, fifth, and sixth transistors have the same transistor characteristics and have a complementary relationship with the transistor characteristics of the third transistor, and the drain of the third transistor is used as the first output signal. 4. A multi-input multi-output logic circuit, characterized in that the drain of the transistor No. 4 is the second output signal.