JPS6029410B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control method for an information processing device having a branch link function and a return function by microprogram control, and its purpose is to control microprogram return when main memory is protected. An object of the present invention is to provide a microprogram control system which improves control processing ability and allows easy and quick access to main memory and a return from a main memory protection check subroutine to a main program.

Here, the branch and link (hereinafter referred to as BAL) function is to temporarily save the return address of the main program when moving from the main program to the subroutine, and then transfer the start address of the subroutine to the microprogram storage device (hereinafter referred to as ROM). The return (hereinafter referred to as RTN) function is associated with the above BAL function, and is a function that enters outside the ROM address register to specify the address of the subroutine. When returning to the main program, the return address of the main program saved by the above-mentioned light AL is input into the ROM address register, and the function of returning to execution of the main program is implemented. Explain an example.

In the figure, 101 is an address generation circuit that generates the start address of the main memory protection check subroutine by receiving the signal S, and 102 is a microprogram that performs sequence control of the microprogram based on the sequence designation by the signals S, , So. Sequencer (hereinafter referred to as pSEQ), 103 is this Yamaichi pSEQI
ROM address register (hereinafter referred to as RAR) provided in 02
104 is a ROM for storing a microprogram that is controlled by the addressing of this RARI03, and 105 is a ROM data register (hereinafter referred to as R
106 is a decoder for decoding the microinstructions stored in RDRI05, 107 is the 7th bit of the program status word (PSW) (PS0
7) Memory protection mode information (“1”) specified for
A first flip-flop (hereinafter referred to as the first flag) 108 that stores the set output "1" of the first flag 107 and the memory write signal (MW) obtained from the decoder 176 are input. When the signal S (''1''
), 109 is the signal S obtained from this AND gate 108 or the above decoder 06
BAL
110 is an AND gate that outputs a BR mode condition signal M2 when the test signal (TEST) and the branch (BR) signal obtained from the decoder 06 are input; 1
1 receives the signals M, , M2 and the RTN signal obtained from the decoder 106, and based on these input signals,
One of four microprogram sequence modes
This is a sequence mode control circuit that outputs a signal S,,So for selecting and specifying a species and supplies it to moopSEQI02.As shown in Table 1, when S,,So="0", the ROM is
Mu PC for incrementing the address (11)
+1 instruction is executed, S,="0", So="1", BAL instruction is executed to save and branch the current address by 11, S,="1", So="0"
RT to move the address waiting in RARI 03 to RARI 03
It issues an N instruction and issues a BR instruction to set an externally given address in RARI03 with S, , S2="1".

Table 1 Also, 112 is a second flip-flop (hereinafter referred to as a second flag) that holds and indexes the main memory access request permitted by the execution of the main memory protection check subroutine, and 113 is this second flag. An AND gate 114 controls the output of the set output (main memory access request) of 112 based on the RTN signal obtained from the decoder 06, and 114 is an AND gate that outputs "0" when the signal S is not output from the AND gate 108. ”
115 is the AND gate 113 which controls the output of a start signal (START) which is obtained from the decoder 106 and instructs the start of memory access.
or an OR gate that outputs a memory access signal AM ("1") by receiving the "1" output of the AND gate 114; 1 1 6 is a write/proceed signal for the main memory obtained from the decoder 06 prior to BAL processing; Main memory cycle mode holding register (hereinafter referred to as MOM) that stores various main memory cycle mode information such as data size (full word, half word, byte) designation signal
R), 1 1 7 is a memory obtained from the OR gate 115, and the M
This is a memory control circuit that performs main memory access control according to the contents of CMRI16.

To explain the BAL operation here, the ROMI04's output (microinstruction) based on the addressing of the RARI03 is stored in the RDRI05.
The contents of DRI05 are output to data lines L and L.

The data via the data line L is sent to the decoder 106 and decoded, and various signals based on the data contents are output. Here, when the BAL signal is output from the decoder 106, this BAL signal is passed through the OR gate 109 to the BAL signal.
It is input to the sequence mode control circuit 111 as the AL mode condition signal M. As a result, the sequence mode control circuit 1 1 1 outputs a signal S, , So (S, = "0", So = "1") indicating the BAL sequence mode, and sets moopSEQI02 to the BAL mode. On the other hand, the data (starting address of the subroutine) via data line L2 is transferred to Yamaichi p via data line -.
It is sent to SEQI02 and input to RARI03. The entrusted operation is a normal BAL operation. Further, in the main memory protection mode, the following BAL operation is performed. In main memory protection mode, the first flag is 10.
7 is set to indicate the main memory protection mode, and at this time, the memory write signal (M
When W) is output, a signal S of "1" level is output from the AND gate 108, and this signal S is sent to the address generation circuit 101 and also to the OR gate 109. As a result, OR Gate 109 sends the above-mentioned normal BAL mode condition signal M,
In response to this signal Mo, the sequence mode control circuit 111 outputs a signal S,, So (S, = "0", So = "1") indicating the BAL sequence mode, and the PSEQI02 becomes BAL. In addition, the address generation circuit 101 is activated based on the signal S, and the start address of the main memory protection check subroutine output from the address generation circuit 101 is MU PSE.
It is sent to QI02 and input to RARI03. On the other hand, M.C.
When executing the BAL mode, the MRI 16 stores various main memory cycle mode information such as a write/proceed signal for the main memory and a data size designation signal when the memory write signal (MW) is output from the decoder 106. . In addition, BAL in the above main memory protection mode
During control, AND gates 1 1 4 are closed, so the start signal (START) is sent from decoder 06.
Even if the main memory access signal A based on this is output
M is not output, and the write mode at this time is the MC that has been entrusted.
Retained on MRI 16. In this manner, when a write instruction is given under the main memory protection mode, execution of the microinstruction instructing the write is prohibited, and the microinstruction is changed to a subroutine jump microinstruction, that is, a BAL instruction. Next, the BAL operation according to the present invention will be explained. First, to explain the normal RTN operation, the decoder 106 decodes the decoder 106 based on the contents of RDRI05.
When the RTN signal is output from 06, this signal is sent to the AND gate 113 and also to the sequence mode control circuit 111. As a result, the sequence mode control circuit 111 outputs a signal S, , So (S, = "1'', So = "0") indicating the RTN sequence mode, and the PSEQI02 becomes the RTN mode, and the BAL mode is set to the above-mentioned BAL mode. The RCM address (main program return address) saved at the time is input to RARI03 and main program processing begins.Normal RTN operation ends here, but BA under the main memory protection mode mentioned above
When a memory access request that has been checked by the main memory protection check subroutine by L is set in the second plug 112 and the flag 112 is in the set state, the set output of this flag 112 is sent to the decoder 106. The output is controlled based on the RTN signal obtained from the memory access signal (AM) via the OR gate 115.
The signal is input to the memory control circuit 117 as a signal. As a result, the memory control circuit 117 uses the MCMRI when executing the main memory protection check subroutine.
The main memory cycle mode stored in 16 thus controls memory access. That is, the second flag 11
When 2 is set and indicates a memory access request, main memory access control is performed in accordance with the RTN operation from the main memory protection check subroutine to the main program. As detailed above, according to the present invention, the RTN operation from the memory protection check subroutine to the main program and the main memory access operation can be executed with one microinstruction, and execution of main memory access in parentheses is flagged. This improves the control processing ability in microprograms, and also improves the processing power of microprograms.

Gram processing time can be shortened.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 101... Address generation circuit, 102... Micro program sequencer (MUPSEQ), 1 03
... Re-ROM address register (RAR), 104
．． ．． ．． ．． 、． ROM, 1 0 5. ...ROM data register (RDR), 106 ... Decoder, 107, 112 ... Flag, 108, 110, 113
, 114...AND gate, 109, 115...OR gate, 116...Main memory cycle mode holding register (MCMR), 117...Memory control circuit.

Claims (1)

[Claims] 1. A mode control circuit that selectively specifies any mode from multiple types of microprogram sequence modes including branch and link mode and return mode, and a microprogram sequencer that executes program sequence processing based on the specifications of this mode control circuit. a flag indicating a main memory access request; a first gate circuit for controlling the output of the main memory access request of the flag by a return signal based on the result of decoding the microinstruction; and an output signal of the first gate circuit or a second gate circuit that obtains a main memory access request signal by receiving a start signal based on a result of decoding a microinstruction; and a memory cycle mode holding circuit that maintains a main memory cycle mode when executing branch and link processing. When a return command is output after execution of branch and link processing, the main memory access request of the above flag is permitted, and main memory access control is performed according to the contents of the memory cycle mode holding circuit based on this main memory access request. A microprogram control method characterized by: