JPS6029411B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control method for an information processing device having a branch and link function and a return function by microprogram control. By smoothing the control and improving processing capacity,
It is an object of the present invention to provide a microprogram control method that allows easy and quick execution of write prohibition to main memory and branching to a main memory protection check subroutine.

Here, the above branch and link (hereinafter referred to as BAL) function, when moving from the main program to a subroutine, temporarily saves the return address of the main program and then stores the start address of the subroutine in a microprogram storage device (hereinafter referred to as ROM). The return (hereinafter referred to as RT) function is ancillary to the above BAL function.
When changing from the subroutine to the main program, the above BA
Set the return address of the main program that was kept waiting at L to R.
A function that inputs data to the OM address register and returns to main program execution.

An embodiment of the present invention will be described below with reference to the drawings. In the figure, 101 is an address generation circuit that generates the start address of the main memory protection check subroutine by receiving the signal S, and 102 is a microprogram that performs sequence control of the microprogram based on the sequence designation by the signals S, , So. Sequencer (hereinafter referred to as r-
PSEQ), 103 is this mu PSEQI0
A ROM address register (hereinafter referred to as RAR) provided in RARI03, 104 is an R for storing a microprogram that is set up and controlled by the addressing of this RARI03.
OM, 105 is a ROM data register (hereinafter referred to as RD) that temporarily stores the microinstructions issued by this ROMI04.
106 is a decoder that decodes the microinstruction stored in this RDRI05, 107 is the 7th bit of the program status word (PSW) (PS07
) Memory protection mode information (“1”) specified by
A first flip-flop (hereinafter referred to as the first flag) 108 that stores the first flag 107 outputs a signal when the set output "1" of the first flag 107 and the memory write signal (MW) obtained from the decoder 106 are input. The signal S (''1''
), and 109 is the signal S obtained from this AND gate 108 or the decoder 106 described above.
By inputting the BAL signal obtained from
OR gate outputting L mode condition signal M, 1 1
0 is B when the test signal (TEST) and the branch (BR) signal obtained from the above decoder 06 are input.
AND gate that outputs R mode condition signal M2, 1
1 1 receives the signals M,, M2 and the RTM signal obtained from the decoder 106, and selects and designates one of the four microprogram sequence modes based on these input signals S,, So. This is a sequence mode control circuit that outputs S,,S, and supplies it to PSEQI02, as shown in Table 1. = “0” and R
French to increment (11) the OM address
PC+1 instruction is given, S,="0", So="1", and BAL instruction is given to wait and branch at the address that is 11 times higher than the current address, S,="1", So]"
0" to issue an RTN instruction to move the standby address to RARI 03, and set B to set the externally given address to RARI 03 with S,,So="1".
This is to issue an R instruction. Table 1I Also, 112 is a second flip-flop (hereinafter referred to as a second flag) that holds and indicates a main memory access request that has been permitted by the execution of the memory protection check subroutine; The AND game controls the set output of the flag 112 (main memory access request) based on the RTN signal obtained from the decoder 106.
G, 114 is set to "0" when the signal S is not output from the AND gate 108, that is, the output of the AND gate 108 is "0".
115 is the AND gate 113 which controls the output of a start signal (START) which is obtained from the decoder 106 and instructs the start of memory access.
or an OR gate that outputs a memory access signal AM ("1") by receiving the "1" output of the AND gate 114; 116 is a write/proceed signal for the main memory obtained from the decoder 106 prior to BAL processing; Main memory cycle mode holding register (hereinafter referred to as MOM) stores various main memory cycle mode information such as data size (full word, half word, byte) designation signal.
R), 1 17 is the MCM based on the memory access signal AM obtained from the OR gate 115.
This is a memory control circuit that performs main memory access control according to the contents of RI 16.

To explain the BAL operation here, the readout output (micro instruction) of ROMI 04 based on the address specification of RARI 03 is stored in RDRI 05, and this R
The contents of DRI05 are output to data lines L and L.

The data is sent to the decoder 106 via the data line L, where it is decoded, and various signals based on the data contents are output.
Here, when the BAL signal is output from the decoder 106, this BAL signal is passed through the OR gate 109 to the sequence mode control circuit 11 as the BAL mode condition signal M.
1 is input. As a result, the sequence mode control circuit 1 1 1 outputs a signal S,, So (S, = "0", So = "1") indicating the BAL sequence mode, and sets the mu PSEQI 02 to the BAL mode. On the other hand, the data via the data line L2 (the first address 5 of the subroutine is transferred to the French-PSEQ via the data line L3)
It is sent to I02 and input to PARI03. The above operation is a normal BAL operation. Further, in the main memory protection mode, the following BAL operation is performed. In the main memory protection mode, the first flag 107 is set to indicate the main memory protection mode. At this time, when the memory write signal (MW) is output from the decoder 106, the AND gate 103 outputs a signal S of “1” level, and this signal S is output to the address generation circuit 10.
1 and is also sent to the OR gate 109.

As a result, the OR gate 109 outputs the second BAL mode condition signal M, as in the normal BAL mode, and this signal M causes the sequence mode control circuit 111 to output the signal S, indicating the BAL sequence mode.
, So (S, = "0", So = "1") is output, and MuPSEQI02 enters the BAL mode.Furthermore, the address generation circuit 101 is activated based on the above signal S, and the address generation circuit 101 outputs the signal. The start address of the main memory protection check subroutine is Yamaichi PSEQI02
and input to RARI03. On the other hand, MCRI1
6 stores various main memory cycle mode information such as a write/read signal for the main memory and a data size designation signal when a memory write signal (MW) is output from the decoder 06 when executing the BAL mode. Furthermore, since the AND gate 114 is closed during BAL control in the main memory protection mode, even if the start signal (START) is output from the decoder 106, the memory accelerator signal AM' based on this is not output. The write mode at this time is the MOMRI 1 6 mentioned above.
is maintained.

In this way, when a write instruction is issued under the main memory protection mode, execution of the microinstruction instructing the write is prohibited, and the subroutine jump microinstruction, that is, BA
Can be changed to L command. As described above, according to the present invention, when a write instruction is given to the main memory under the main memory protection mode, the process of prohibiting writing to the main memory and jumping to the main memory protection check subroutine is performed in the first step. This can be done with a single microinstruction, which simplifies microprogram processing and shortens program processing time.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 101...Address generation circuit, 102...
Microprogram sequence (MuPSEQ), 10
3...・ROM address register (RAR), 1
04...ROM, 1 0 5...RO
M data register (RDR), 106... Decoder, 107, 1 12... Flag, 108, 110,
113,114...and gate, 109,115...
OR gate, 116...Main memory cycle mode holding register (MCMR), 117...Memory control circuit.

Claims (1)

[Claims] 1. A mode control circuit that selectively specifies any mode from multiple types of microprogram sequence modes including branch and link mode and return mode, and a microprogram sequencer that executes program sequence processing based on the specifications of this mode control circuit. a flag indicating the main memory protection mode; and a first gate circuit configured to output and control the main memory write request signal based on the result of decoding the microinstruction when the flag indicates the main memory protection mode. A second gate circuit configured to set the mode control circuit to a branch and link mode designation state in response to a branch and link designation signal based on the output signal of the first gate circuit or the result of decoding the microinstruction.
a gate circuit, an address generation circuit that outputs the start address of the main memory protection subroutine based on the output signal of the first gate circuit, and a memory cycle mode that maintains the mode of the main memory cycle when executing branch and link processing. and a holding circuit, and when a main memory write request occurs under main memory protection mode, the microprogram sequence mode is set to branch-and-link mode, and the execution of the main memory protection subroutine is controlled. method.