JPS6029978B2 - Check device - Google Patents

Description

[Detailed Description of the Invention] This invention provides a central processing unit (hereinafter referred to as CPU)
In a control device consisting of a memory device, an input/output device, and a memory device, a failure of the memory device is detected and at the same time the CPU
The purpose is to detect a failure in the input/output data bus (common connection line) that connects the memory device and the input/output device, and to prevent the control device from malfunctioning due to a failure in the memory or input/output data bus. It is something to do.

In addition, if the above-mentioned control device malfunctions, it will take time to analyze the cause of the malfunction of the control device by clarifying whether it is related to the memory or the input/output data bus. This has the effect of shortening the time. In a conventional so-called stored program type control device, a CPU is connected to a large number of input/output devices in addition to a memory device via an input/output data bus.

In this case, as a failure diagnosis method for the control device, the memory device uses a detection method such as a parity check. Software-based processing is often used for other parts, but this method requires a large amount of memory and control time to completely detect failures, and it is difficult to process in real time. However, this method has the disadvantage of reducing the control ability of the control device. In addition, with the above method, even if it is known that there is a failure somewhere in the control device as a whole,
In many cases, it is not possible to determine exactly which device it is. FIG. 1 shows a basic block diagram of a stored program control system. To explain FIG. 1, 1 is a CPU, 2 is a memory device, 31, 32-3n are input devices, 41, 42-4n are output devices, 5 is an input data bus buffer, 6 is an output data bus buffer, 7 is a parity generator, 8 is a parity check device, 9 is a memory address line, 10 is a bidirectional bus, 11 is a CPU output data bus, 12 is a CPU input data bus, 13 is an output data validity bit, 15 is a Timing signal from CPUI I, 161, 162-16n are input signal lines from external equipment, 181, 182-18n are output signal lines from output device to external equipment, 191, 192-19M
Selection signal lines 171, 172 to 17n of the output device are selection signal lines of the input device. Conventionally, errors in the memory device 2 have been detected using a parity generator 7, a parity check device 8, etc., but there is no suitable detection method for the input data bus 12 and output data bus 11. Instead, they relied on the software method described above.

In this case, there were problems such as an increase in the number of memory devices, a decrease in control ability, and a large amount of time required to analyze a defective location.

The present invention solves these conventional problems and uses a parity generator, a parity check device, and a simple gate circuit for checking a memory device, and has a relatively simple configuration with little increase in hardware. The present invention provides a check device that can reliably detect defects in memory devices and input/output data buses with a long response time.

The checking device of the present invention will be explained in detail below with reference to FIG. FIG. 2 shows an embodiment of this invention. In Figure 2, 1, 2, 31-3n, 41-4n, 5, 6
,7,8,9,10,11,12,13,14,15,
161-16n, 171-17n, 181-18n, 1
91 to 19n are the same as those explained in FIG.
Reference numeral 131 is a signal line that is the same as the parity bit 13 of the output data and sends this signal directly to the parity check device. Reference numeral 20 is a gate that sends the signal of the output data bus to the input data bus when necessary. Next, the operation of this invention will be explained.

In FIG. 2, data from an external device is input to the input device 3.
1 to 3n, and data from the memory device 2 is directly transmitted to the input data bus 12. At this time, the data of the only input device selected by input device selection signals 171 to 17n (generated from the CPU) or the data of the memory selected by the memory address line 9 is transmitted to the input data bus 12. be done. This data signal is transmitted to the CPUI via the input data buffer 5, and is also transmitted to the output data bus 11 via the output data buffer 6.
It can also be conveyed. Since the output device selection signal is not generated at this time, it is not transmitted to the external output device and the memory device 2. The signals on the input data bus 12 are simultaneously input to the parity generator 7 and the parity check device 8. At this time, parity bit 13 is generated from parity generator 7 and transmitted to parity check device via signal line 131. When inputting from the memory device 2, the parity bit 14 of the memory is transmitted to the parity check device 8. These two types of parity bits 14 and 131 are selected by a timing signal 15 issued from the CPUI to perform fault diagnosis.

Further, when outputting data to an external device or a memory device, the gate of the input data bus buffer 5 is closed and the gate 20 is opened in response to a timing signal 15 from the CPUI.

At this time, the output data from the CPUI is output from the output devices 41 to 4n.
, or output device selection signals 191 to 19n to the memory device 2
Data is transmitted via the output data bus 11. At this time, the output data simultaneously passes through the gate 20 and is transmitted to the input data bus 12. At this time, since the input device selection signals 171 to 17n are not generated, there is no risk of data being tampered with. The data on the input data bus 12 is transmitted to the parity check device 8, the data on the output data bus 11, and the parity generator 7, and the parity bits 13, 131 generated by the parity generator 7 are transmitted to the memory device 2 and the parity generator 7. It is transmitted to the check device 8, and the CPU
Fault diagnosis is performed using the timing signal 15 from I. As described above, by comparing the data on the input data bus 12 and the data on the output data bus 11, failures in the input/output bus can be diagnosed, and failures in the memory device 2 can also be diagnosed at the same time. If either the input data bus or the output data bus or the memory device fails, the parity check device generates an alarm signal.

In addition, if the timing at which the parity check device issues an alarm signal is when the CPU outputs it to an external device, when it inputs it from an external device to the CPU, or when it inputs it from the closing device to the CPU, the alarm signal can be issued. It is possible to distinguish whether the signal is generated due to an abnormality in the input data bus, the output data bus, or the memory device. Moreover, the check can be performed in real time without affecting the control time of the CPU. As is clear from the above description, the check device of the present invention can detect and detect malfunctions in the input/output data bus and memory device in a so-called stored program type control device. Erroneous control can be prevented.

In addition, only a simple parity generator, a check device, and a simple gate are required as components, requiring little additional hardware, long detection operations, and reliable detection in real time, which has many practical advantages. be.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of conventional stored program type control, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a CPU, 2 is a memory device, and 3
1, 32 to 3n are input devices, 41, 42 to 4n are output devices, 5 is an input data bus buffer, 6 is an output data bus buffer, 7 is a parity generator, 18 is a parity check device, 9 is a memory address line, 10 is the bidirectional bus, 1 1 is the CPU output data bus, 12 is the CPU input data bus, 13 is the output data parity bit, 1
4 is the parity bit of the memory, 15 is the timing signal from the CPUI, 161, 162-16n is the input signal line from the external device, 171, 172-17n is the selection signal line of the input device, 181, 182-18n is the output device 191, 192 to 19n are output device selection signal lines, 131 is a signal line that directly sends the parity bit of 13 to the parity check device of 8, and 20' is an output data bus as necessary. 11 data to the input data bus 12. In the figures, the same reference numerals indicate the same or equivalent parts. 1st
Figure 2

Claims (1)

[Claims] 1. An input data bus that transfers data input via a plurality of input devices and data read from the memory, and an output data bus that transfers data output via a plurality of output devices and data written to the memory. , a data check device in a control unit comprising the input and output data bus, and a central processing unit that inputs and outputs data and controls reading and writing of the memory; a check circuit that checks for errors in data on either the input data bus or the memory using check bits of the generator and timing control of the central processing unit; A check device comprising: a gate for transferring data on the output data bus to the input data bus under timing control.