JPS6030133B2 - digital phase control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase control device that controls the phase purely digitally.

Conventionally, a PLL (phase locked loop) has often been used as a phase control device.

FIG. 1 shows the basic configuration of such a PLL. The phase comparator 1 generates an output voltage corresponding to the phase difference between the input signal ln and the output signal ln2 of the VC○ (voltage controlled oscillator) 2. The low-pass filter 3 integrates and smoothes the output voltage of the phase comparator 1, and outputs a continuous control voltage corresponding to the phase difference. The VC02 is low pass filter 3
The oscillation frequency is controlled by the control voltage output by. In this way, in the PLU, the phase difference is converted into the output of the low-pass filter 3, but the output of the low-pass filter 3 fluctuates due to the leakage of the capacitor constituting the filter 3.

Therefore, the PLL has the disadvantage that highly accurate phase control cannot be performed due to the influence of the characteristics of the capacitor. The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a digital phase control device that can perform highly accurate phase control by controlling the phase in a purely digital manner.

An embodiment of the present invention will be described below with reference to the drawings.

In FIGS. 2 and 3, the phase difference to be corrected detected by the phase difference detection means (not shown) is output from the same phase difference detection means to the data bus as a phase displacement amount a. When correcting the phase, the phase displacement amount a output on the data bus is held in the phase displacement amount Hall register 4 at the rising edge of clock b when clock b is output from a control section (not shown). be done. Note that the data bus length is arbitrary, but if it is assumed to be 8 bits as an example here, the phase displacement amount a has a range of 0 to 255. The register 4 inputs the input phase variable a to be corrected to the scale conversion memory 5 as a register output c.

The scale conversion memory 5 is a bit conversion memory for converting the phase displacement amount a into a frequency division amount for presetting a phase displacement counter 7, which will be described later.
×N/255 bit conversion is performed. Here, N' is the frequency division ratio of the clock frequency division counter 6, ie, the reference counter, which will be described later. As an example, if N is 180, then given address J, (180/255)
Information for outputting J is written in the scale conversion memory 5. Therefore, 180 is output for the maximum phase displacement amount a, 255. In this way, the phase displacement amount a that has been bit-converted into a frequency division amount by the scale conversion memory 5 is outputted from the same memory 5 as an output d, and is used as preset data for the phase displacement counter 7 that counts the amount of phase movement. is entered as . The time delay of the memory output d with respect to the register output c in FIG. 3 is the execution time within the memory 5. Presetting of the phase displacement counter 7
The data is loaded into the counter 7 when the load signal e for the phase displacement counter turns ON' (a negative logic signal becomes "LoW").

Further, the counter 7 outputs a carry signal f when the number of clocks of the system clock i input from the oscillator 8 to the counter 7 after the load signal e turns ON' matches the value of the preset data. . On the other hand, the preset value h of the clock frequency dividing counter 6, which receives the system clock i from the oscillator 8, is adjusted to the desired clock frequency.

The load signal of the clock frequency dividing counter 6 is obtained by multiplying the carry signal g of the counter 6 and the carry signal f of the phase displacement counter 7 by an OR circuit 9. The clock frequency division counter 6 counts the number of input system clocks i, and when the counted value matches the preset value h', it outputs a carry signal g, while the load signal is input. Each time the system clock i is counted, the value counted up to that point is cleared and the system clock i is counted again from the initial state.

Now, the desired timing clock can be obtained from the carry signal g, but if phase correction is not performed, there is no carry signal f and the clock division counter 6 is loaded only by the carry signal g. The period of the signal g is T, as shown between the clock 1 and the clock plate in FIG.

Furthermore, when phase correction is performed, the carry signal g is controlled as follows.

That is, when the number of clocks of the system clock i counted by the phase displacement counter 7 matches the preset value of the counter 7, that is, the phase displacement amount converted to the frequency division amount, a carry signal f is output, and this is used as the clock signal. Since it is loaded into the frequency division counter 6, the clock frequency division counter 6 clears the value it was counting halfway and starts counting the system clock i again from the initial state, and as a result, the carry signal g is The phase is corrected according to the phase difference, and the period is set to T2 as shown between clocks m and W in FIG. The corrected phase amount in this case corresponds to -T. As described above, the digital phase control device according to the present invention converts the phase displacement amount into a frequency division amount using the scale conversion memo IJ, and corrects the phase of the timing clock with this frequency division amount, thereby controlling the phase in a purely digital manner. is controlled, enabling highly accurate phase control, and since memory is used to convert the phase displacement amount to the frequency division amount,
This has the excellent effect of reducing the number of elements and increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional PLL, FIG. 2 is a block diagram showing a digital phase control device according to an embodiment of the present invention, and FIG. 3 is a signal waveform diagram showing the operation of each part of the device. 5... Scale conversion memory, 6... Clock frequency division counter, 7... Phase displacement counter, 8... Oscillator. Figure 1 Figure 3 Figure 2

Claims (1)

[Claims] 1. In a digital phase control device having a digital phase control loop, a high frequency oscillator, a frequency divider that divides the output of the high frequency oscillator by N and uses the divided output signal as a phase signal, and a phase difference detection means that receives feedback from the phase difference detection means. A scale conversion memory that divides the phase difference M of the output of the frequency divider and converts it into M'(N≧M'), and a clock frequency division counter that counts M' output clocks of the high frequency oscillator. A digital phase control device characterized in that the phase is changed in proportion to the change in the phase difference M by initializing the frequency divider with a carry signal of the clock frequency division counter.