JPS6031124B2 - Arithmetic amplifier - Google Patents
Arithmetic amplifierInfo
- Publication number
- JPS6031124B2 JPS6031124B2 JP50126577A JP12657775A JPS6031124B2 JP S6031124 B2 JPS6031124 B2 JP S6031124B2 JP 50126577 A JP50126577 A JP 50126577A JP 12657775 A JP12657775 A JP 12657775A JP S6031124 B2 JPS6031124 B2 JP S6031124B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- value
- circuit
- multiplier
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—DC amplifiers in which all stages are DC-coupled
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明はトランジスタを含んで構成された差動増幅器と
入力側及び出力側聞に位相補償用コンデンサが接続され
てなる増中器とが縦続接続されてなる演算増中器の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides an arithmetic multiplier in which a differential amplifier including transistors and a multiplier in which a phase compensation capacitor is connected between the input side and the output side are connected in cascade. Concerning the improvement of utensils.
斯種演算増中器の原理的構成は、第1図に示す如く、例
えば2つのNPN型のトランジスタQI及びQ2を有し
、之等トランジスタQI及びQ2のコレクタが夫々直流
電流を通し得る負荷例えば抵抗RI及びR2を通じて電
源接続端子laに、ェミッタが互に接続されて電源接続
端子laと対をなす電源接続端子lbに夫々接続され、
而してトランジスタQI及びQ2のベースより夫々入力
端子2a及び2bが、又トランジスタQI及びQ2の何
れか一方例えばトランジスタQ2のコレクタより出力端
子2cが夫々導出されてなる構成の差動増中器3と、例
えば1つのPNP型トランジスタQ3を有し、そのェミ
ッタが直接的に電源後続端子4aに、コレクタが直流を
通し得る負荷例えば抵抗R3を通じて電源端子4bに夫
々接続され、又ベース及びコレクタより夫々入力端子5
a及び出力端子5cが導出されてなる構成を有する増中
器6とを有し、而して差動増中器3の電源接続端子la
及び増中器6の電源接続端子4aが電源7の正極性側の
端子8aに、差動増中器3の電源接続端子lb及び増中
器6の電源接続端子4bが電源7の負極性側の端子8b
に夫々接続され、又差動増中器3の出力端子2cが増中
器6の入力端子5aに接続され、一方増中器6の入力側
及び出力側聞に位相補償用コンデンサ9が接続され、更
に差動増中器3の入力端子2a及び2bより夫々演算増
中器としての入力端子10a及び10bが、増中器6の
出力端子5cより同様に演算増中器としての出力端子1
0cが夫々導出せる構成を有するものである。As shown in FIG. 1, the basic structure of this type of operational multiplier includes, for example, two NPN type transistors QI and Q2, and the collectors of the transistors QI and Q2 are connected to a load, for example, through which DC current can pass. The emitters are connected to the power supply connection terminal la through the resistors RI and R2, and the emitters are connected to the power supply connection terminal lb, which is paired with the power supply connection terminal la, respectively;
The differential amplifier 3 has a configuration in which the input terminals 2a and 2b are led out from the bases of the transistors QI and Q2, respectively, and the output terminal 2c is led out from the collector of one of the transistors QI and Q2, for example, the collector of the transistor Q2. and, for example, one PNP type transistor Q3, the emitter of which is directly connected to the power supply trailing terminal 4a, the collector of which is connected to the power supply terminal 4b through a load capable of passing direct current, such as a resistor R3, and the base and collector of which are connected to the power supply terminal 4b, respectively. Input terminal 5
a and a multiplier 6 having a configuration in which the output terminal 5c is led out, and the power supply connection terminal la of the differential multiplier 3
The power supply connection terminal 4a of the multiplier 6 is connected to the positive polarity side terminal 8a of the power supply 7, and the power supply connection terminal lb of the differential multiplier 3 and the power supply connection terminal 4b of the multiplier 6 are connected to the negative polarity side of the power supply 7. terminal 8b of
The output terminal 2c of the differential multiplier 3 is connected to the input terminal 5a of the multiplier 6, while a phase compensation capacitor 9 is connected between the input side and the output side of the multiplier 6. Furthermore, the input terminals 2a and 2b of the differential multiplier 3 are connected to input terminals 10a and 10b as operational multipliers, respectively, and the output terminal 5c of the multiplier 6 is connected to output terminal 1 as an operational multiplier.
It has a configuration in which 0c can be derived respectively.
又斯る原理的構成を有する演算増中器は、ある周波数(
これをfcとする)以下の範囲に於ては、定電流駆動し
ている差動増幅器は差動入力電圧をコレクタ電流に変換
する伝達コンダクタンス増幅器として動作するので、差
動増幅器3の伝達コンダクタンスをgm,差動増中器3
の電源接続端子lbを流れる電流を13、増中器6の電
流利得をa6、出力端子10cに接続される負荷の値を
RLとするきA,=gm・86・RL・………”【11
gm=q.13/k・T………………■
で表わされる(但しqは電子の電荷、kはポルツマン定
数、Tは絶対温度で表わされる差動増中器3の外囲温度
を示す)比較的高い電圧利得の値A,を有し、周波数f
c以上に於ては、周波数fc以上の周波数を一般にfm
とし、又位相補償用コンデンサ9の容量をC9とすると
きふニgm/2汀fmC9……………【3ーで表わされ
る周波数fmが高くなるに従い直線的に低下せる電圧利
得の値んを有する第2図に示す如き周波数f−電圧利得
A特性を呈するものである。Moreover, an operational intensifier with such a principle configuration has a certain frequency (
In the following range (denoted as fc), the differential amplifier driven at a constant current operates as a transconductance amplifier that converts the differential input voltage into collector current, so the transconductance of the differential amplifier 3 is gm, differential multiplier 3
When the current flowing through the power supply connection terminal lb is 13, the current gain of the multiplier 6 is a6, and the value of the load connected to the output terminal 10c is RL, then A, = gm・86・RL・……”[ 11
gm=q. 13/k・T………………■ (where q is the electron charge, k is Polzmann's constant, and T is the ambient temperature of the differential multiplier 3 expressed in absolute temperature). has a high voltage gain value A, and has a frequency f
For frequencies above fc, frequencies above fc are generally fm
And when the capacitance of the phase compensation capacitor 9 is C9, the value of the voltage gain that decreases linearly as the frequency fm increases, expressed as fm/2 fmC9...[3-] It exhibits a frequency f-voltage gain A characteristic as shown in FIG.
所で斯る演算増中器は種々の演算装置の回路素子として
利用されているが、その利用態様は第2図の周波数−電
圧利得特性でみて周波数fc以下の周波数範囲で利用さ
れる場合、周波数fc以上の周波数範囲で利用される場
合、周波数fc以下及び以上の両範囲に跨がつて利用さ
れる場合が存し、而して何れの周波数範囲で利用される
にせよ、電源7の電圧及び外囲温度の変化に依存せざる
電圧利得が得られることが望まれるものである。By the way, such arithmetic multipliers are used as circuit elements in various arithmetic devices, but the manner in which they are used is when they are used in a frequency range below frequency fc, as seen in the frequency-voltage gain characteristics shown in Fig. 2. When used in a frequency range above frequency fc, there are cases where it is used across both the range below frequency fc and above fc, and regardless of which frequency range it is used, the voltage of power supply 7 It is also desirable to be able to obtain a voltage gain that is independent of changes in ambient temperature.
然し乍ら、電源7の電圧が変動すれば之に応じて13の
値が変化し、又差動増中器3の外囲温度が変化すれば之
に応じてTの値が変化し、そして電圧利得Aの値が‘1
}及び‘3’式に示す如く、13及びTを含む■式で与
えられるgmに依存するので、電圧利得Aの値は何等か
の手段を講じない限り電源7の電圧及び差動増中器3の
外園温度の変化に依存することとなるものである。However, if the voltage of the power supply 7 changes, the value of 13 changes accordingly, and if the ambient temperature of the differential multiplier 3 changes, the value of T changes accordingly, and the voltage gain The value of A is '1
} and '3', the value of the voltage gain A depends on the gm given by the equation This will depend on the change in the outside temperature in step 3.
特に演算増中器を周波数fc以上の周波数範囲又はその
範囲を含む周波数範囲で利用する場合、‘3}式で表わ
される電圧利得Aの値A2の変化が問題となるものであ
る。尚1}式で表わされる電圧利得Aの値A,の電源7
の電圧及び差動増中器3の外囲温度に対する変動は、電
圧利得Aの値A,自体比較的大なる値を有し、一方一般
に演算増中器を回路素子として利用せる演算装置の演算
特性でみた電源電圧及び外囲温度の変化に影響される項
が、演算増中器の電圧利得Aを分母とせる関係を有する
ので左程問題とはならないものである。この為即ち糊式
で表わされる電圧利得Aの値んが電源7の電圧及び差動
増中器3の外圏温度の変化に依存せんとするを補償すべ
く従来種々の提案がなされているが未だ満足し得るもの
ではなかつた。In particular, when the operational amplifier is used in a frequency range above frequency fc or in a frequency range that includes this range, a change in the value A2 of voltage gain A expressed by equation '3' poses a problem. Note that the power supply 7 with the value A of the voltage gain A expressed by the formula 1}
The variation with respect to the voltage of the voltage and the ambient temperature of the differential multiplier 3 is the value A of the voltage gain A, which itself has a relatively large value. Since the term affected by changes in the power supply voltage and ambient temperature in terms of characteristics has a relationship in which the voltage gain A of the operational amplifier is used as the denominator, this is not as much of a problem. For this reason, various proposals have been made in the past to compensate for the fact that the value of the voltage gain A expressed by the glue equation does not depend on the voltage of the power supply 7 and the outer temperature of the differential multiplier 3. It still wasn't something I was satisfied with.
叙上に鑑み本発明は、特に上述せる電圧利得Aの値A2
が電源7の電圧及び差動増中器3の外囲温度の変化に依
存せんとするを有効に補償する様にした斯種演算増中器
を提案せんとするもので、差動増中器の相互コンダクタ
ンスgmの値が上述せる電流13の値に比例し、一方上
述せる温度Tの値に逆比例するので、電流13の値を電
源7の電圧変化に対しては無関係ならしめた状態でその
電流13の値を温度Tの値が大なるに応じて相互コンダ
クタンスgmの値が減少する分増加せしめれば、相互コ
ンダクタンスgmの値が電源7の電圧及び差動増中器3
の外囲温度の変化せんとするを補償し得、そして斯くg
mの値が補償されれば、電圧利得Aの値A2が電源7の
電圧及び差動増中器3の外因温度の変化せんとするを補
償し得るということに着目せるものであり、第3図につ
いて本発明の実施例を詳述する所より明らかとなるであ
るつo第3図に於て第1図との対応部分には同一符号を
附して詳細説明はこれを省略するも、例えば1つのPN
P型のトランジスタQ4を有し、そのコレク夕及びェミ
ッ夕が夫々電源接続端子21a及び21bに接続され、
又ベースより制御端子22が導出されてなる定電流回路
23が設けられ、而し0てこの定電流回路23がその電
源接続端子21a及び21bを夫々差動増中器3の電源
接続端子lb及び電源7の端子8bに懐続せる関係で葦
動増中器3の電源接続端子lb及び電源7の端子8b間
に介挿されている。In view of the above, the present invention particularly provides a value A2 of the voltage gain A mentioned above.
The purpose of the present invention is to propose such an operational multiplier that effectively compensates for the dependence of the voltage on the power supply 7 and the ambient temperature of the differential multiplier 3. Since the value of the mutual conductance gm is proportional to the value of the current 13 mentioned above, and inversely proportional to the value of the temperature T mentioned above, the value of the current 13 is made to be independent of the voltage change of the power supply 7. If the value of the current 13 is increased by the amount that the value of the mutual conductance gm decreases as the value of the temperature T increases, the value of the mutual conductance gm will change depending on the voltage of the power supply 7 and the differential multiplier 3.
can compensate for changes in the ambient temperature of g, and thus g
It is noted that if the value of m is compensated, the value A2 of the voltage gain A can compensate for changes in the voltage of the power supply 7 and the external temperature of the differential multiplier 3. As will become clear from the detailed description of the embodiments of the present invention with regard to the figures, in FIG. 3, corresponding parts to those in FIG. For example one PN
It has a P-type transistor Q4, the collector and emitter of which are connected to power supply connection terminals 21a and 21b, respectively,
Further, a constant current circuit 23 having a control terminal 22 led out from the base is provided, and the constant current circuit 23 connects the power supply connection terminals 21a and 21b to the power supply connection terminals lb and 21b of the differential multiplier 3, respectively. It is inserted between the power supply connection terminal lb of the reed action multiplier 3 and the terminal 8b of the power supply 7 so as to be connected to the terminal 8b of the power supply 7.
又例えば2つのPNP型トランジスタQ5及びQ6と1
つのNPN型トランジスタQ7とを有し、トランジスタ
Q5のェミッタが直接的に電源接続端子24aに接続さ
れ、ベースが抵抗25を通じて電源接続端子24aに接
続され且トランジスタQ6のェミッタに直接的に接続さ
れ、コレク夕が直接的にトランジスタQ6のベースに接
続され且直流負荷26を通じて電源接続端子24aと対
をなす電源接続端子24bに接続され、又トランジスタ
Q6のコレク夕が直接的にトランジスタQ7のベースに
接続され且抵抗27を通じてトランジスタQ7のコレク
タに接続され、更にトランジスタQ7のェミッタが直接
的に電源端子24bに接続され、コレククタより出力端
子28が導出されてなる構成の制御回路29が設けられ
、而してこの制御回路29の電源端子24a及び24b
が夫々電源7の端子8a及び8bに、出力端子28が定
電流回路23の制御端子22に夫々接続されている。尚
この場合の直流負荷26はソースより一方の接続端子を
、ゲート及びドレィンより之等互に接続されて他方の出
力端子を夫々導出せる鞍合型電界効果トランジスタ30
を適用し得るものである。以上が本発明の一例構成であ
るが、斯る構成は、差動増中器3の電源接続端子lbが
電源7の端子8bに直接的に接続されるに代え定電流回
路23を通じて接続され、一方定電流回路23が制御回
路29にて制御される様になされていることを除いては
第1図の場合と同様であるので、斯る構成によっても第
2図にて上述せる周波数−電圧利得特性が得られること
明らかであるが、差動増中器3の電源接続端子lbに流
れる電流13‘ま、定電流回路23で適用せるトランジ
スタQ4の逆方向飽和電流をls4、トランジスタQ4
のベース・ェミッタ間に与えられる電圧をV4とすると
き、ー3:IS4eXp(k台・V4).・・.・・.
・・・…・で与えられる。For example, two PNP transistors Q5 and Q6 and 1
the emitter of the transistor Q5 is directly connected to the power supply connection terminal 24a, the base is connected to the power supply connection terminal 24a through the resistor 25, and directly connected to the emitter of the transistor Q6; The collector is directly connected to the base of the transistor Q6, and is connected to the power supply connection terminal 24b that is paired with the power supply connection terminal 24a through the DC load 26, and the collector of the transistor Q6 is directly connected to the base of the transistor Q7. A control circuit 29 is provided, which is connected to the collector of the transistor Q7 through the resistor 27, further has the emitter of the transistor Q7 directly connected to the power supply terminal 24b, and has an output terminal 28 led out from the collector. Power terminals 24a and 24b of the lever control circuit 29
are connected to terminals 8a and 8b of power supply 7, respectively, and output terminal 28 is connected to control terminal 22 of constant current circuit 23, respectively. In this case, the DC load 26 is a saddle-type field effect transistor 30 whose one connection terminal is connected to the source, and whose gate and drain are connected to each other so that the other output terminal can be led out.
can be applied. The above is an example of the configuration of the present invention. In such a configuration, the power supply connection terminal lb of the differential multiplier 3 is connected to the terminal 8b of the power supply 7 through the constant current circuit 23 instead of being connected directly to the terminal 8b of the power supply 7, On the other hand, since it is the same as the case in FIG. 1 except that the constant current circuit 23 is controlled by the control circuit 29, the above-mentioned frequency-voltage in FIG. It is clear that a gain characteristic can be obtained, but the current 13' flowing to the power supply connection terminal lb of the differential amplifier 3, the reverse saturation current of the transistor Q4 applied by the constant current circuit 23, is ls4, and the transistor Q4 is
When the voltage applied between the base and emitter of is V4, -3: IS4eXp (k level V4).・・・.・・・.
It is given by...
この場合V4は制御回路29の出力端子28従ってトラ
ンジスタQ7のコレクタ及び電源接続端子8b間で得ら
れる電圧に等しく、トランジスタQ7のベース及びェミ
ッタ間に与えられる電圧をV7、トランジスタQ6のコ
レクタ電流をL、抵抗27の値をR7とし、トランジス
タQ7のベース電流を無視すれば(このベース電流はk
‘こ比し十分小であるので無視し得る)、V4;V7−
R了・16..・..・..・・….・【5}式で与え
られ、一方16は、トランジスタQ7の逆方向飽和電流
をIS?とすればにIS7eXp(k古・V7).・・
.・….・・…・で与えられるが、トランジスタQ5の
ベース・ェミッ夕間電圧をVBE5 、抵抗25の値を
R5とし、トランジスタQ6のベース電流を無視すれば
(このベース電流もち‘こ比し十分小であるので無視し
得る)、L=VBE5/R5…・・…・・・・・・・{
7)で与えられるので、(5)式に【7}式を代入すれ
ばV4はV4=V7−亀VB曲‐‐‐‐‐‐‐‐‐‐‐
‐‐‐‐{8’で与えられる。In this case, V4 is equal to the voltage obtained between the output terminal 28 of the control circuit 29 and hence the collector of the transistor Q7 and the power supply connection terminal 8b, V7 is the voltage applied between the base and emitter of the transistor Q7, and L is the collector current of the transistor Q6. , if the value of the resistor 27 is R7 and the base current of the transistor Q7 is ignored (this base current is k
'It is sufficiently small compared to this so it can be ignored), V4; V7-
R completed・16. ..・.. ..・.. ..・・・・・・.・It is given by the formula [5}, while 16 is the reverse saturation current of the transistor Q7 IS? If so, IS7eXp (k old/V7).・・・
..・…. ..., but if the base-emitter voltage of transistor Q5 is VBE5, the value of resistor 25 is R5, and the base current of transistor Q6 is ignored (this base current is sufficiently small compared to ), L=VBE5/R5......{
7), so by substituting equation [7} into equation (5), V4 is V4=V7-Turtle VB song-----------
‐‐‐‐{8' is given.
依って{4)式を(6ー式、【7}式及び■式を用いて
13について解けば(但しIS4 =ls7とする)、
ln13ilnVBE5−台‐VBE5‐受−lnR5
‐‐‐….・・……‘91(ここで、lnは自然対数を
表している)が得られる。Therefore, if we solve equation {4) for 13 using equations (6-, [7} and ■) (however, IS4 = ls7),
ln13ilnVBE5-unit-VBE5-reception-lnR5
‐‐‐.... ...'91 (here, ln represents the natural logarithm) is obtained.
従って差動増中器3の電源端子lbに流れる電流13‘
ま外囲温度Tには依存するも、電源7の電圧変化に対し
ては無関係となるものである。所で電流らの外園温度T
に対する依存性をみるに、【9}式をTに関して微分す
れば、÷.d13−
,3dT−点・d等費−亨・溝十蔓・台
(寧等)肌側
なる関係が得られ、そして剛式右辺の第1項はトランジ
スタQ5のベース・ェミッタ間電圧VBE5の温度係数
に起因し従って一般に負の値を呈し、又第2項は抵抗2
5の温度係数に起因しそしてこの抵抗25の温度係数は
この抵抗25を半導体基板内への不純物の拡散により形
成する場合トランジスタQ5のベース・ェミッタ間電圧
VB85 の温度係数の絶対値より十分小なる絶対値を
有する正の値を呈し、従って皿式の右辺の第1及び第2
項による値は負となり、一方【10}式の第3項は常に
正の値となるので、R7/R5の比を適当に選べば、電
流13‘ま外圏温度Tに対して正の温度係数を有する依
存性を有することとなる。Therefore, the current 13' flowing through the power supply terminal lb of the differential multiplier 3
Although it depends on the ambient temperature T, it is unrelated to changes in the voltage of the power supply 7. At the place, the outdoor temperature T
Looking at the dependence on T, if we differentiate equation [9} with respect to T, we get ÷. The following relationship is obtained: d13-, 3dT-point, d-equivalent cost-Toru, Mizojutsutsu, Tai (Ning, etc.) skin side, and the first term on the right side of the rigid equation is the temperature of the base-emitter voltage VBE5 of transistor Q5. coefficient and therefore generally takes a negative value, and the second term is due to the resistance 2
5, and the temperature coefficient of the resistor 25 is sufficiently smaller than the absolute value of the temperature coefficient of the base-emitter voltage VB85 of the transistor Q5 when the resistor 25 is formed by diffusing impurities into the semiconductor substrate. exhibits a positive value with an absolute value, and therefore the first and second on the right side of the dish equation
The value due to the term is negative, while the third term in equation [10} is always a positive value, so if the ratio of R7/R5 is chosen appropriately, the current 13' will have a positive temperature with respect to the outer sphere temperature T. This results in a dependence with a coefficient.
今斯る関係をR7/R5の比の値をパラメータとして温
度Tに対するもの関係を図示すれば第4図に示す如くに
なるものである。依って第4図の曲線でみて例えば符号
Mで示す如き曲線が得られるべくR7/R5の比の値を
適当に選べば、その曲線Mが直線性を有する外園温度T
の範囲Ta〜Tbに於て、電流13の値は外囲温度Tが
大なるに応じて大となり、従って上述せる(2}式に基
き外囲温度Tが大なるに応じて差動増中器3の相互コン
ダクタンスgmが小となるも、13が大となってgmが
大となり、結局gmはTa〜Tbの外囲温度Tが変化し
てもその変化範囲で略々一定となるものである。If this relationship is plotted against temperature T using the value of the ratio R7/R5 as a parameter, it will be as shown in FIG. 4. Therefore, if the value of the ratio of R7/R5 is appropriately selected so as to obtain a curve as shown by the symbol M in the curve shown in FIG.
In the range Ta to Tb, the value of the current 13 increases as the ambient temperature T increases, and therefore, based on the above equation (2), the value of the current 13 increases as the ambient temperature T increases. Although the mutual conductance gm of vessel 3 becomes small, gm becomes large as 13 becomes large, and in the end gm remains approximately constant within the range of change even if the ambient temperature T of Ta to Tb changes. be.
上述せる如く、上述せる本発明の一例構成に依れば、差
動増中器3の相互コンダクタンスgmの値が電源7の電
圧及び差動増中器3の外園温度の変化せんとするを補償
し得るので、特に上述せる‘3)式で表わされる電圧利
得Aの値ふが電源7の電圧及び差動増中器3の外圏温度
の変化せんとするを補償し得る演算増中器が得られるこ
ととなる大なる特徴を有するものである。As described above, according to the exemplary configuration of the present invention described above, the value of the mutual conductance gm of the differential multiplier 3 compensates for changes in the voltage of the power supply 7 and the temperature outside the differential multiplier 3. Therefore, in particular, the value of the voltage gain A expressed by the above-mentioned equation '3) is an arithmetic intensifier that can compensate for changes in the voltage of the power supply 7 and the outer atmosphere temperature of the differential intensifier 3. It has great features that will be obtained.
尚上述に於ては本発明の一例を示したに過ぎず、差動増
中器3、増中器6、定電流回路23及び制御回路29の
構成も図示せる構成に限定されることなく図示せる構成
を基礎としてこれより種々の変型変更をなした構成とし
得るものである。The above description merely shows one example of the present invention, and the configurations of the differential multiplier 3, the multiplier 6, the constant current circuit 23, and the control circuit 29 are not limited to those shown in the drawings. Based on the configuration shown, various modifications and changes can be made from this configuration.
第1図は本発明の基礎となる演算増中器の一例を示す接
続図、第2図は本発明の説明に供する演算増中器の周波
数−電圧利得特性を示す図、第3図は本発明に依る演算
増中器の一例を示す接続図、第4図はその説明に供する
外圏温度に対する差動増中器の電源端子に流れる電流の
関係を示す曲線図である。
図中、QI〜Q7はトランジスタ、la,lbは電源接
続端子、2a及び2bは入力端子、3は差動増中器、6
は増中器、7は電源、9は位相補償用コンデンサ、23
は定電流回路、29は制御回路を夫々示す。
第2図
第4図
図
船
第3図FIG. 1 is a connection diagram showing an example of an operational amplifier that is the basis of the present invention, FIG. 2 is a diagram showing the frequency-voltage gain characteristics of the operational amplifier used to explain the present invention, and FIG. FIG. 4 is a connection diagram showing an example of the operational multiplier according to the invention, and FIG. 4 is a curve diagram showing the relationship between the current flowing through the power supply terminal of the differential multiplier with respect to the outer atmosphere temperature, to provide an explanation thereof. In the figure, QI to Q7 are transistors, la and lb are power supply connection terminals, 2a and 2b are input terminals, 3 is a differential amplifier, and 6
is an intensifier, 7 is a power supply, 9 is a phase compensation capacitor, 23
2 shows a constant current circuit, and 29 shows a control circuit. Figure 2 Figure 4 Figure Ship Figure 3
Claims (1)
側及び出力側間に位相補償用コンデンサが接続されてな
る増幅器とが縦続接続され、かつ、前記差動増幅器のト
ランジスタを定電流駆動するための定電流回路が電源に
直列に挿入され、該定電流回路を通じて流れる電流が制
御回路によつて制御される演算増幅器において、前記制
御回路が前記電源に接続された抵抗及びトランジスタを
含み、前記定電流回路の温度係数を正とする第1の回路
と前記定電流回路の温度係数を負とする第2の回路の縦
続接続から成り、第1の回路に含まれる抵抗の値と第2
の回路に含まれる抵抗の値との比が前記差動増幅器の伝
達コンダクタンスの温度係数が零となるように設定され
たことを特徴とする演算増幅器。1 A differential amplifier including transistors and an amplifier including a phase compensation capacitor connected between the input side and the output side are connected in cascade, and the transistors of the differential amplifier are driven with a constant current. In an operational amplifier in which a constant current circuit is inserted in series with a power supply, and a current flowing through the constant current circuit is controlled by a control circuit, the control circuit includes a resistor and a transistor connected to the power supply, and the constant current It consists of a cascade connection of a first circuit whose temperature coefficient is positive and a second circuit whose temperature coefficient of the constant current circuit is negative, and the value of the resistance included in the first circuit and the second circuit are connected in series.
An operational amplifier, characterized in that a ratio between the value of the resistor included in the circuit and the temperature coefficient of the transfer conductance of the differential amplifier is set to zero.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50126577A JPS6031124B2 (en) | 1975-10-21 | 1975-10-21 | Arithmetic amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50126577A JPS6031124B2 (en) | 1975-10-21 | 1975-10-21 | Arithmetic amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5250147A JPS5250147A (en) | 1977-04-21 |
| JPS6031124B2 true JPS6031124B2 (en) | 1985-07-20 |
Family
ID=14938602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50126577A Expired JPS6031124B2 (en) | 1975-10-21 | 1975-10-21 | Arithmetic amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6031124B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3801923A (en) * | 1972-07-11 | 1974-04-02 | Motorola Inc | Transconductance reduction using multiple collector pnp transistors in an operational amplifier |
-
1975
- 1975-10-21 JP JP50126577A patent/JPS6031124B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5250147A (en) | 1977-04-21 |
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