JPS603206B2 - Sequence controller shift register device - Google Patents

Description

[Detailed Description of the Invention] Instead of a sequence controller configured with relays or non-contact relays, the present invention stores sequences in a storage device in the form of logical expressions, and changes to the sequence can be made by simply modifying the storage device. The present invention relates to a shift register device suitable for use in a sequence controller that can be easily operated.

The shift register is suitable for use in, for example, an article sorting device that transports multiple types of articles on one conveyor and unloads them from different outlets depending on the type of article. be.

FIG. 1 shows an outline of an example of this, in which 1 is a conveyor driven in steps by a step-drive electric motor 2, A and B each represent a different article, and 3 is an article A.
4 is the outlet for article B. 5 is conveyor 1
This is an article discriminator installed near the entrance of the article discriminator, which is configured to output a detection pulse from terminal 5a when article A passes in front of it, and output a detection pulse from terminal 5b when article B passes in front of it. It has been done.

The conveyor 1 has addresses A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, , , , , , , , , , , , , , , , , , , , , , , , , ,
In the case of the figure, "The article discriminator 5 is installed at address Ao, and the exit 3 and address A are installed at address Ao."
5 and 4 are installed respectively. 6 and 7 are registers, and each register goes to the address of conveyor 1, A,...
. . . The register 6 receives a signal from the terminal 5a as a serial input, and the register 7 receives a signal from the terminal 5b as a serial input.

Each of the registers 6 and 7 uses a signal from a step drive signal generator 8, which generates a step signal every time the motor 2 drives the comparator by one step, as a shift-up signal. In this way, the article discriminator 5 sends a pulse signal to the register 6 when determining the article A, and sends a pulse signal to the register 7 when determining the article B. Moreover, every time the conveyor 1 is driven step by step, each register 6
, 7 will shift up. FIG. 2 is a state diagram showing this state, and each bit 0, 1, 2, .
The contents of No. 6 are shown in a different form. In this case, the state in FIG. 1 corresponds to a step number of four. That is, article A
Since A0 is located at the address, the 0 bit and 4 bit of the register 6 logically store the state of "1", and it is stored that the article A is located at the address Ao of the conveyor 1. Similarly, register 7 stores the state where bit 1 is logically '11' and stores that article B is at address A on conveyor 1. Therefore, bit 4 of register 6 is logically '11'.
If the outlet 3 is opened at the point where the value becomes ``1'', the article A can be unloaded from the outlet 3, and the article A can be unloaded at the point where bit 5 of the register 7 logically becomes ``1''. If you open mouth 4, article B
can be dropped from this outlet 4. In this way, even if different articles are randomly placed at the entrance of the conveyor 1, the articles can be reliably sorted. When the control part of such a sorting device is configured with the above-mentioned sequence controller, conventionally a shift register is installed as an external device of the sequence controller, and information is exchanged between them to control the opening and closing of the outlet. I was doing it.

FIG. 3 shows the state, where 10 is the sequence controller main body and 11 is a shift register. 1
2 is an input circuit of the sequence controller 10, 13 is an output circuit, and the serial input terminal a, shift up terminal b, and clear terminal C of the shift register 1 are connected to the success circuit 13
Operate on the output of the output terminal ○ to change the logic state of the required bit.
The input circuit 12 takes in the data from the input circuit 12, and this input is used as logical operation data for the sequence controller 10.

In a sequence controller, the input/output circuit portion accounts for a considerable portion of the price, and an increase in the number of input/output circuits directly affects the price. However, when a shift register is installed externally like a slave, shift register 1
For one operation, at least three output circuits and one input circuit are required for one shift register. In addition, in the case of the above-mentioned sorting device, it is necessary to allocate one piece to each type of article, and depending on the number of types of articles, it is necessary to allocate one piece to each type of article. It is common for it to extend. Therefore, a considerable amount of man-hours are spent on the wiring between the shift register and the sequence controller, the arrangement of the shift register, etc., and the shift register uses a considerable part of the sequence controller's input/output circuit, making the entire system The drawback was that it was expensive. In addition, in view of these shortcomings, shift registers have been constructed using software, but this requires considerable knowledge and complicates the program, resulting in reduced program memory. A considerable portion of the device is owned by the program that configures the shift register.

Therefore, unless a program storage device is added, other control programs cannot be stored, and the program storage device cannot be used effectively. The present invention has been made in view of the above circumstances, and eliminates the need for man-hours such as wiring and installation when adding shift registers, and it is possible to minimize the number of input/output circuits used in the sequence controller. To provide a shift register for a sequence controller which can be operated with a simple program and can effectively utilize a program storage device.

In order to achieve the above object, the present invention is characterized by sequentially reading out instruction codes stored in a plurality of addresses in a program storage device, and instructing a logical operation processing unit to execute the logic of the input/output circuit specified by the operand part of the instruction code. A sequence in which states are sequentially input, logical operations specified by the operation section of the instruction code are executed sequentially, the logical operation results are stored in the corresponding output circuit, and the corresponding control target is controlled by the contents of this world power circuit. The controller has an area for storing shift information, shift-up operation signal detection information, and serial input information at each address, and the operation section stores the contents of the address specified by the operand part of the instruction code that has a shift command or shift-up command. It inputs a random access memory to output, a first register that stores and outputs the contents output from this random access memory, and an operation section for an instruction code, and if this is a shift instruction, a shift instruction signal is input. and a command decoder that outputs a shift-up instruction signal if it is a shift-up command, and temporarily stores and outputs the logic state of the external device that constitutes the serial signal input means when executing a shift command, and executes the shift-up command. a second register that temporarily stores and outputs the logic state of an external device constituting the shift-up signal input means, and a shift-up operation signal detection information of the output of the first register; and the decoder outputs a shift-up instruction signal to match these two inputs, and there is a change in logic state between these two inputs, and the output of the second register is a shift-up operation signal output determiner that outputs the shift-up operation signal only when it is in the logical state that outputs the shift-up signal;
The shift command signal, the shift-up command signal, the shift-up operation signal, the output information of the second register, and any bit of shift information within the address specified by the operand part of the instruction code when executing the shift command. a conversion circuit that inputs designated bit designation information, converts the storage contents of the first register according to these inputs, and outputs the converted contents so that the contents can be stored in a predetermined location of the random access memory; By receiving the shift command signal, the output of the second register is made into serial input information, and the shift information and the shift-up operation signal detection information are outputted as they are. The shift information is the information shifted by the serial input information, the output of the second register is used as shift-up operation signal detection information, and the serial input information is output as is, and the shift-up command is output. When a signal is received but a shift-up operation signal is not received, the output information of the second register is used as shift-up operation signal detection information, and the serial information and shift information are output as they are.

An embodiment of the present invention shown in FIG. 4 will be described below.

Reference numeral 20 denotes a program storage device, in which instruction codes consisting of an operation section and an operand section are stored at each of a plurality of addresses.

Addresses of the program storage device 20 are sequentially specified by an address specifying means (not shown), and instruction codes are sequentially read out. Reference numeral 21 denotes an instruction decoder, which inputs an operation section of an instruction code and outputs a signal from a predetermined state of the output terminal OP according to the contents thereof.

12 is an input circuit which inputs the operand part of the instruction code and connects to the input terminal lo at the address specified by this operand part.
, 1, , 12, . . . , ln.

13 is an output circuit which inputs the operand part of the instruction code and outputs the output terminal ○o at the address specified by this operand part.
, 0, 02, . . . , 0n, or outputs a logic state signal of the controlled object.

Reference numeral 22 denotes a logical operation processing device, which inputs the signal from the output terminal OP of the instruction decoder 21 and the output signals of the input/output circuits 12 and 13, executes a predetermined logical operation, and outputs the logical operation result. .

This result is stored at an arbitrary address of the output circuit 13 designated by the operand part of the instruction code. The output circuit 13 then controls and operates the corresponding control object according to the content. When the instruction codes are sequentially read from the program storage device 20, the instruction decoder 21 and the input/output circuit 12,
13, signals are sequentially applied to the logic processing unit 22. The logic processing unit 22 sequentially takes in these signals,
A predetermined operation is executed and the result is stored at each designated address of the output circuit 13. Then, each terminal oo of the output circuit 13
, 0,, 02, . The above is a general sequence controller, and the following is a shift register device configured according to the present invention. 23 is a random access memory, and each of the plural addresses has shift information Do, D,, D2, . . . , Dn- as shown in FIG.
, shift-up operation signal detection information Mo, serial input information M, and output information M2.

This memory 23 is addressed by the operand part of the instruction code read from the program storage device 20, and outputs the contents of the address. 24 are shift-up operation signal detection information Mo from the random access memory 23, serial input information M, output information M2, and shift information Do.
, D, , D2, . . . , Dn-, and outputs the temporarily stored data.

The instruction decoder 21 decodes the shift instruction SD and outputs the terminal SDT.
outputs a shift command signal SDS from the terminal SUT, decodes the shift up command SU, and outputs a shift up command signal S from the terminal SUT.
Configure to output US. Note that although the instruction decoder 21 also serves as the instruction decoder for decoding the shift instruction SD and shift-up instruction SU, it may be provided separately. In the case of the embodiment, the logical operation processing device 22
is also used as the second register. Therefore, when executing the shift instruction SD, the logical operation processing device 22 is connected to an external device constituting a serial signal input means connected to an arbitrary terminal of the input circuit 12 specified by the operand part of the instruction code, such as the article discriminator in FIG. Any situation 5
a, 5b are temporarily stored and output, and when the shift-up command SU is executed, the logic state of an external device constituting the shift-up signal input means, for example, the step drive detector 8 in FIG. 1, is temporarily stored and output. It is configured to output. 25 is a shift-up operation signal output determiner;
Shift-up operation signal detection information M among the outputs of the first shift register 24.

and the output information CO from the logic processing unit 22, and by applying the shift-up command signal SUS, these two inputs Mo and CO are compared and determined. and,
The shift-up operation signal SHS is output only when there is a change in the logic state between the information Mo and CO and the information CO is in the logic state in which the shift-up signal was output. For example, when the information Mo is logically "0" and the information CO is logically "1", the shift-up operation signal SHS which is logically "1" is output. During the cycle of generating serial signals and shift-up signals, for example, the signals of the article discriminator 5 and the step drive detector 8, and the time of the generated signals, the program storage device 20 is accessed once by the address specifying means. Much longer than the specified cycle time. Therefore, while one shift-up signal is being generated, the address detection means scans the shift command and shift-up command multiple times, resulting in shift information being shifted multiple times.
Therefore, only the rising edge of the shift-up signal is detected using the shift-up operation signal SHS, and the shift information is thereby shifted. 26 is a shift command signal SDS, a shift up command signal SUS, a shift up operation signal SHS, the output information CO of the logic processing unit 22, and the address specified in the operand part of the instruction code when executing the shift command SD. Shift data Do, D,
, D2, . . . , Dn-, and inputs bit designation information m that designates specific bits of , D2, . The output information of this conversion circuit 26 is sent to the Langmuth access memory 23 and stored within the original address. FIG. 6 is a diagram showing how the conversion circuit 26 converts and outputs the output contents of the first register 24 according to the combination of information and signals input thereto, where a is a shift This shows the conversion state when the instruction SD is executed, and b indicates the case where the shift-up operation signal SUS is generated when the shift-up instruction SU is executed, and the case where the shift-up operation signal SUS is not generated when the shift-up instruction SU is executed. is shown in c. In each of FIGS. 6a, b, and c, the upper row shows the state before conversion, and the lower row shows the state after conversion. The conversion circuit 26 is composed of data selectors 27, 28, 29 and a shifter 30. The data selector 27 is the logical operation processing unit 22
The output information CO and the output shift-up operation signal detection information pigeon of the first register 24 are input, and when the shift-up command signal SUS is added, information CO is selected, and when this is not added, information Mo is selected. , and outputs the selected information as an information location for shift-up detection. The data selector 28 inputs the output information CO of the logic processing unit 22 and the serial input information M of the output of the first register 24, selects the information CO by adding the shift command signal SDS, and selects the information CO when this is not added. This selects information M, and outputs the selected information as serial input information M,'. The data selector 29 selects shift information D from the first register 24 such as D, , D2,
..., Dn-, the output information M2, and the bit designation information m from the program storage device 20, and by adding the shift command signal SDS, the shift information Do, D is input.
,,D2,...,Dn-, selects the m-th bit information specified by bit designation information m, selects output information M2 by not adding this, and selects the selected information as output information M2. Output. Shifter 3, shift information Do, D,, D2,..., D from the first register 24
n-, and the serial input information M, and by adding the shift operation signal SHS, the shift information Do, D
,,D2,...,Dn-, is shifted by 1 bit using serial input information, and the information is converted into shift information〇o,〇,,〇2,...,D
If this is not added, the shift information Do, D,, ○2, ..., Dn-, is output as the shift information D'o, 〇,, D'2, ..., 〇n-, as is. Output. Its structure is as shown in FIG. 6 or FIG. 7, for example. FIG. 7 shows how the switching circuit 31 is set to shift information D.
It is constructed by using the number of bits of D,,D2,...,Dn-, and each circuit 31 has shift information Do.
,D,,D2,...,Dn-, and serial input information M
, are input as shown in the figure, and this circuit 31 is switched by the shift-up operation signal SHS. Then, by adding the shift-up operation signal SHS, the serial input information M, is output as 〇, and the other information is output as 1.
The data is shifted bit by bit and outputted as Do becomes 0, D becomes D'2, and so on. FIG. 8 uses a shift register 32, in which a shift-up operation signal SHS is input to a shift-up terminal 32a via a pulse oscillator 33, and shift information Do, D,, D2,..., Dn- is serially transmitted. Shift up with input information M. Figure 9 and 1
FIG. 0 is a time chart and state change diagram for explaining the operation of the embodiment of the present invention.

In FIG. 9, SI indicates the serial input, SUP indicates the shift-up input, and INS indicates the time point at which the shift command and shift-up command stored in the program storage device 2 are executed in this order, and this interval To is always constant, and this interval To corresponds to the cycle time described above. 10th
The figure shows the contents of the output information of the conversion circuit 26 at time points to, t, t2, . . . , [6 in FIG. 9. The operation will be described below with reference to these figures.

In the description, it is assumed that the following two command expressions are stored at a certain address in the program storage device 20. SD(
N, m)=X,.

...01SU(N) =×2.
...■These formulas are stored in the program storage device 2.
0 is stored in machine language, but for convenience of explanation, it is shown like this. The '1' formula is a shift command, N is the address of the random access memory 23, m is bit designation information, X and o are input devices connected to the input terminals 1 and o of the input circuit 13, such as the article in FIG. Either the output terminal 5a or 5b of the discriminator 5 is shown. In other words, this formula takes logic information from the input device connected to terminals 1 and o of the input circuit 13 as serial input to the shift register assigned to address N of the random access memory 22, and outputs the m-th bit of the shift register. It means to give instructions as follows. Equation (2) is a shift up command, N is the address of the random access memory 22 as before, and the number X is an input device connected to the input terminal 13o of the input circuit 13, for example, the step drive detector in FIG. That is, this formula is based on the logic information from the input device connected to the terminal 1 of the input circuit 13.
This means instructing to shift up the shift register assigned to address N. It is assumed that the random access memory 23 has been cleared and all contents are logically "0". It is assumed that the shift information is composed of 5 bits, and the bit information m specifies the third bit.
Note that FIG. 10 shows shift command SD and shift up command S.
Although the instructions are shown as if they are executed simultaneously, the instructions are actually executed in the order of shift instruction SD and shift up instruction SU. In the program storage device 20, addresses are sequentially specified in a short time by the address specifying means, and instruction codes are sequentially output.

The logical operation unit 22 sequentially takes in logical information from the input/output circuits 12 and 13 specified by the operand part of the instruction code, sequentially executes the logical operations specified by the operation part, and outputs the logical results to the specified output circuit. Send to 13th. Due to the characteristics of the sequence controller, the time required for the address designation means to designate the last address from the first address of the program storage device 20, that is, the cycle time, is determined by the serial input SI.
Or it is much earlier than the period or time of the shift up input SUP. In this way, the address detection means repeatedly specifies the address of the program storage device 20 at high speed. now,
Assume that the address specifying means specifies the address of the program device 20 storing the above-mentioned m-formula. Then,
The instruction code is read out, the operation section is input to the instruction decoder 21, and the operand section specifies address N of the random access memory 23. As a result, the command decoder 21 outputs the shift command signal SUS from the terminal SDT. At the same time, the contents of address N of the random access memory 23 are stored in the first register 24. At this point, input circuit 1
Since the serial signal ST is not applied to the input terminals 1 and o of the converter 2, all bits of the information output from the conversion circuit 26 are logically "0" as shown in FIG. is stored at address N. Subsequently, when the formula (2) is read from the program storage device 23, the information stored at address N is stored in the first register 24.
is stored in This formula is a shift-up command, and since the shift-up signal SUP is added to the input terminal 12o, the output information CO of the logic processing unit 22 becomes logically "1", and the shift-up operation signal detection information Mo. Since the previous state is logically "0", the shift-up operation signal detection circuit 25 outputs the shift-up operation signal SUS which is logically "1". Therefore, Fig. 6b
Therefore, the output of the conversion circuit 26 is that the shift-up signal detection information Mo is logically "1" and the others are logically "0". After that, the shift up signal SUP is input to the input terminal 1, o.
As long as the information stored at address N remains unchanged. Next, when the '1} expression is read from the program storage device 20 at time t, this expression is a shift instruction SD, and input terminal 1,. Since the serial input SI is not added to SI, from FIG.
”.Subsequently, when the '2-formula is read out, the output information CO becomes logically "0", so the conversion circuit 26
All output information becomes logically "0". Thereafter, even if the shift command SD and shift-up command SU are executed, the information content at address N of the random access memory 23 remains unchanged as long as there is no change in the serial signal SI and shift-up signal SUP. Next, when the '1} formula is read out at time t2, the serial signal SI is input to input terminal 1,
o, and the output information CO of the logical operation processing unit 22 becomes logically "1". The output information of the conversion circuit 26 is
From Figure a, serial input information Mo is logically "1" and all others are logically "0". Subsequently, when the formula ■ is read out, a shift up input SUS is applied to the input terminal 12o.
is added, the output information of the logical operation processing unit 22 becomes logically "1". Since the previous state of the shift-up operation signal detection information Mo is logically "0", the shift-up operation signal output determination circuit 25 outputs the shift-up operation signal SHS. Therefore, Fig. 6b
Therefore, the shift information Do, D, . Bit ◯ of D2, . Hereinafter, as shown in FIG. 10, as time passes, the serial input SI becomes the shift-up signal SHS.
is added and shifted sequentially at time points t6 and t8. In the above example, if you want to output the third bit of the shift register assigned to the N address of the random access memory 23, an output instruction is stored in the program storage device 20 in advance, and this instruction outputs the output information of the N address. This content is then sent to a predetermined location of the output circuit 12 designated in advance, for example, through the logic processing unit 22 as shown in the figure. Then, this signal is applied from the output terminal to, for example, the exit opening/closing device of the example shown in FIG. 1 to control opening/closing. In the above embodiment, for convenience of explanation, the random access memory 23
Although the explanation has been made for one address N in the random access memory 22, it is possible to allocate a plurality of addresses in the random access memory 22 as each register, and to connect an external device that configures serial input and a shift-up input to each address. If each is determined, this shift register device acts as a plurality of register devices.

Furthermore, in the embodiment, an area for storing the output information M2 is provided at each address of the random access memory 22, but this area may be omitted if the corresponding address and corresponding bit are specified when outputting. . Furthermore, the description of the example is '
We have explained the case where the left side of equation 1) and equation '2' inputs the logic state of the input device connected to a specific terminal of the input circuit 12, but in this case, the logic state of multiple input devices is input. may be logically operated using a predetermined logical formula, and the serial input and shift-up input may be determined based on the results. That is, the left-hand sides of the expressions '1} and (2) may be logical algebraic expressions, which can be fully realized with the prior art. Furthermore, although the random access memory 23 and the two program storage devices are provided separately, a part of the program storage device 20 may be used as the random access memory 23. As is clear from Father's explanation,
According to the present invention, each address of the random access memory can be used as a shift register, so the address of the random access memory is specified in the program storage device, and the instruction code for operating the shift register allocated to this address is stored. Shift registers can be added with a simple operation, and the effect is that there is no need for man-hours for wiring, installation, etc. for addition.

Furthermore, since direct control can be performed from the program storage device without going through an input/output circuit, the use of the input/output circuit of the sequence controller can be minimized, and expensive input/output circuits can be used effectively. Furthermore, since the device of the present invention can be operated with simple commands such as a shift command and a shift-up command, the program can be simplified and control operations can be performed with a small number of words in the program storage device, so the program storage device can be used effectively. This has the effect of allowing more control programs to be stored and a wider range of control.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing a column using shift registers in an article sorting device, Fig. 2 is a state change diagram showing the process of changing the memory contents of the shift register shown in Fig. 1, and Fig. 3
The figure is a schematic diagram showing an example of a case where a shift register is installed externally in a sequence controller, Figure 4 is a block wiring diagram showing an embodiment of the present invention, and Figure 5 is a diagram showing the word configuration of a random access memory. , Figure 6 shows the conversion circuit 2
6 is a diagram showing how the output information is converted by input information and signal combinations, FIGS. 7 and 8 are diagrams showing an example of the configuration of the shifter 30, and FIG. In order to explain the operation of the embodiment of the present invention, the serial input SI
A time chart showing the relationship between the shift-up input SUP, the shift command, and the execution cycle of the shift-up command, 1st
Figure 0 is the time point to, t,,; t2,..., t8 in Figure 9.
3 is a diagram showing a state change of the output information of the conversion circuit 26 after completion of instruction execution in FIG. 12...Input circuit, 13...Output circuit, 20...
. . . Program storage device, 21 . . . Instruction decoder, 22 .
...first register, 25...shift-up operation signal output determiner, 26...conversion circuit, M...shift-up operation signal detection information, M. ......Serial input information, Do, D,, D2,..., Dn-.・・・
...Shift information. Doro/Zu Doro 2 drawings j plans 7 drawings 6 drawings 4 younger brother drawings 5 younger brother chi drawing younger brother noku drawings

Claims (1)

[Claims] 1 Read instruction codes stored in multiple addresses in a program storage device sequentially, input logical states of input/output circuits specified by the operand part of the instruction code into the logic processing unit sequentially, In a sequence controller that executes logical operations sequentially, stores the logical operation results in the corresponding output circuit, and controls the corresponding control target using the contents of this output circuit, shift information and shift-up operation signal detection information are stored at each address. a random access memory that has an area for storing serial input information and a shift instruction or a shift up instruction and outputs the contents of the address specified by the operand part of the instruction code having a shift instruction or shift up instruction in the operation section; and the contents output from this random access memory. a first register that temporarily stores and outputs the instruction code, and an instruction decoder that inputs the operation part of the instruction code and outputs a shift command signal if the instruction is a shift instruction, or outputs a shift up instruction signal if the instruction is a shift up instruction. a second device which temporarily stores and outputs the logic state of the external device constituting the serial signal input means when executing the shift command, and temporarily stores and outputs the logic state of the external device constituting the shift up signal input means when the shift up command is executed; A register, shift-up operation signal detection information among the outputs of the first register, and output information of the second register are input, and the decoder outputs a shift-up instruction signal, thereby receiving both inputs. a shift-up operation signal output determiner that outputs a shift-up operation signal only when there is a change in logic state between these two inputs and the output of the second register is in the logic state that outputs the shift-up signal;
specifying the shift command signal, the shift up command signal, the shift up operation signal, the output information of the second register, and any bit of shift information within the address specified by the operand part of the instruction code when executing the shift command; and an exchange circuit for inputting bit designation information, exchanging the stored contents of the first register according to these inputs, and outputting the exchange circuit so that the contents can be stored in a predetermined location of the random access memory. By receiving the shift command signal, the output of the second register is made into serial input information, and the shift information and shift-up operation signal detection information are output as they are. By receiving the serial input information, the shift information is the information shifted by the serial input information, the output of the second register is used as information for detecting the shift-up operation signal, and the serial input information is output as is, and the shift-up command signal is output. When the shift-up operation signal is not received, the output information of the second register is used as the shift-up operation signal detection information, and the serial information and shift information are output as they are.