Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS6032977B2 - semiconductor envelope - Google Patents
[go: Go Back, main page]

JPS6032977B2 - semiconductor envelope - Google Patents

semiconductor envelope

Info

Publication number
JPS6032977B2
JPS6032977B2 JP8716976A JP8716976A JPS6032977B2 JP S6032977 B2 JPS6032977 B2 JP S6032977B2 JP 8716976 A JP8716976 A JP 8716976A JP 8716976 A JP8716976 A JP 8716976A JP S6032977 B2 JPS6032977 B2 JP S6032977B2
Authority
JP
Japan
Prior art keywords
metal
semiconductor chip
insulating plate
insulating
envelope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8716976A
Other languages
Japanese (ja)
Other versions
JPS5313360A (en
Inventor
功一 藤沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP8716976A priority Critical patent/JPS6032977B2/en
Publication of JPS5313360A publication Critical patent/JPS5313360A/en
Publication of JPS6032977B2 publication Critical patent/JPS6032977B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体チップを電気絶縁性、熱良導性の薄板を
介して放熱預金属体に支持させるようにする半導体外囲
器の改良に係わり、特に熱伝導性の比較的低い絶縁薄板
の使用も可能にして低価格化をはかろうとするものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a semiconductor envelope in which a semiconductor chip is supported on a heat dissipation deposit metal body through an electrically insulating and thermally conductive thin plate. The aim is to reduce costs by making it possible to use relatively inexpensive thin insulating plates.

半導体装置、例えば高周波トランジス外こおいては、そ
のチップの底面を構成している電極、例えばプレーナ形
トランジスタにおけるコレクタを放熱用金属体より電気
的に絶縁することが有利であり、これが各種の容量分、
前記のように底面電極がコレクタの場合には出力容量を
増加させないためであることはよく知られている。
In semiconductor devices, such as high-frequency transistors, it is advantageous to electrically insulate the electrodes that make up the bottom of the chip, such as the collector in a planar transistor, from the metal body for heat dissipation. minutes,
It is well known that this is because when the bottom electrode is a collector as described above, the output capacitance is not increased.

一方高出力トランジスタでは、チップ内で発生する熱を
チップ底面より外囲器放熱体を経て放散させることが必
要である。これら2つの理由のために従来高周波高出力
トランジスタではパイポーラ形およびュニポーラ形を含
めてその外囲器は熱伝導性がよく、かつ電気絶縁性のよ
い薄板を介して半導体チップを放熱用金属体に支持させ
るように構成されている。
On the other hand, in a high-output transistor, it is necessary to dissipate heat generated within the chip from the bottom surface of the chip through an envelope heat sink. For these two reasons, conventional high-frequency, high-output transistors, including bipolar and unipolar types, have an envelope that has good thermal conductivity and a thin plate with good electrical insulation to connect the semiconductor chip to a metal body for heat dissipation. It is configured to support.

第1図および第2図はこのように構成された従来の外囲
器を示すのであって、放熱体に結合支持される放熱用金
属体がスタツド1、止めねじ用孔のあいた平板11で構
成され、これらに電気絶縁性で熱良導体の例えば円板2
,12の一面が接着され、他面に入力端子となる金属帯
3,13、出力端子と金属帯4,14、接地端子となる
金属帯5,5′(第1図の場合のみ)が接着されている
。接地端子は第2図に示すように円板12に形成した金
属膜15,15′で構成し、これを放熱用平板11に接
続してもよい。第1図に示すようにトランジスタ構造を
なす半導体チップ7は入力、出力または接地用金属帯中
の例えば出力用金属帯4上に接着され、他の金属帯3,
5,5′とチップ内の電極とは細線8,9,9′で接続
されている。このような半導体チップ7を外雰囲気から
防護するためには、例えば第1図に示すように円板2と
ほぼ同径のセラミック製のキャップ状蓋体6を円板に接
着して半導体チップを含むキャップ内部を外雰囲気と遮
断するか、また第2図に示すように合成樹脂材16でモ
ールド封止する。上記の電気絶縁性でかつ熱良導体とし
ては、通常酸化ベリリウムセラミックから成るべリリア
が用いられているが、本物質の粉末は皮ふ毒として知ら
れており、製造的に不利で高価となる欠点がある。使用
するべリリアの量を少なくする工夫をした構造としては
第3図に示すようなものがある。
FIGS. 1 and 2 show a conventional envelope constructed in this manner, in which the heat dissipating metal body coupled and supported by the heat dissipating body consists of a stud 1 and a flat plate 11 with a hole for a set screw. These are electrically insulating and thermally conductive, such as a circular plate 2.
, 12 are glued on one side, and on the other side are glued the metal strips 3 and 13 that will serve as input terminals, the output terminals and metal strips 4 and 14, and the metal strips 5 and 5' that will serve as ground terminals (only in the case of Figure 1). has been done. The grounding terminal may be constructed of metal films 15, 15' formed on the disk 12, as shown in FIG. 2, and may be connected to the heat dissipating flat plate 11. As shown in FIG. 1, a semiconductor chip 7 having a transistor structure is bonded on one of the metal strips for input, output, or grounding, for example, an output metal strip 4, and other metal strips 3,
5, 5' and the electrodes in the chip are connected by thin wires 8, 9, 9'. In order to protect such a semiconductor chip 7 from the external atmosphere, for example, as shown in FIG. The inside of the cap containing the cap is isolated from the outside atmosphere or is molded and sealed with a synthetic resin material 16 as shown in FIG. Berylia, which is made of beryllium oxide ceramic, is usually used as the electrical insulator and thermal conductor mentioned above, but the powder of this substance is known as a skin poison, and it has the disadvantage of being disadvantageous and expensive in terms of manufacturing. be. A structure designed to reduce the amount of Beryllia used is shown in FIG. 3.

すなわち放熱用スタッド21の上面周囲に電気絶縁性電
極支持環27を暖着し、この上面に入力金属帯23、出
力金属帯24、接地金属帯25,25′を接着する。環
27の内部には電気絶縁性、熱良導性円板22を配置し
、放熱用スタッド21の上面に接着する。円板22の上
面は半導体チップを接着するために金属膜28を形成し
ておくことが必要であり、この金属膜は何れかの金属帯
例えば出力金属帯24と紬線29にて接続される。円板
22上の金属膜28上に接着された半導体チップ内の電
極は適当な上記金属帯と細線で接続される。半導体チッ
プの外雰囲気との遮断は、例えばセラミック製のキャッ
プ状蓋体26を環27の金属帯接着面に接着することに
より達成できる。電気絶縁性で熱良導体となる物質とし
てのべリリアは大きな熱伝導率(〜0.4cal/cm
s℃)と過大でない比誘電率(〜7)とを有して好まし
いものであるが、上記のようにその粉末が皮ふ奏である
ため、加工性に問題があり、ベリリアを用いた外囲器は
高価なものとなる欠点を有する。本発明はかかる事情に
鑑みてなされ、比較的熱伝導率の低い物質を用いて、放
熱用効果がよく構成も容易で価格の低廉な半導体外囲器
を提供しようとするものである。
That is, the electrically insulating electrode support ring 27 is warmly attached around the upper surface of the heat dissipation stud 21, and the input metal band 23, the output metal band 24, and the ground metal bands 25, 25' are adhered to this upper surface. An electrically insulating and thermally conductive disk 22 is placed inside the ring 27 and adhered to the upper surface of the heat dissipation stud 21. It is necessary to form a metal film 28 on the upper surface of the disk 22 in order to adhere the semiconductor chip, and this metal film is connected to any metal band, such as the output metal band 24, by a pongee wire 29. . Electrodes in the semiconductor chip bonded onto the metal film 28 on the disk 22 are connected to appropriate metal bands using thin wires. The semiconductor chip can be isolated from the outside atmosphere by bonding, for example, a ceramic cap-like lid 26 to the metal band adhesive surface of the ring 27. Beryllia, which is an electrical insulator and a good thermal conductor, has a high thermal conductivity (~0.4 cal/cm).
s°C) and a not-excessive dielectric constant (~7), but as mentioned above, the powder is skin-like, so there is a problem with workability, and an envelope using beryllia has the disadvantage of being expensive. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor envelope that uses a material with relatively low thermal conductivity, has good heat dissipation effects, is easy to construct, and is inexpensive.

以下本発明の詳細をその一実施例を示す第4図によって
説明する。すなわち半導体チップを載置させるに足りる
程度の幅で比較的薄い厚さを有する放熱用絶縁板32が
放熱用金属板31上に接着され、この絶縁板32より厚
く、これを挟むようにその側面に接して絶縁物片36,
36′を放熱用金属板31上に接着し、入出力金属帯3
3,34を絶縁物片の上面に接着する。接地は例えば放
熱用絶縁板の両端部に金属化により形成した金属膜35
,35′と接続して達成される。半導体チップの接着個
所は放熱用絶縁板32の上面のほぼ中央に選び、ここま
で入出力金属帯または接地金属膜の何れかを延長する。
図示の例では出力金属帯34を延長している。この延長
部分と放熱用絶縁板32とは熱的に良好に接着すること
を要する。半導体チップの外雰囲気との遮断は、絶縁板
32と絶縁物片36,36′とで形成された凹部37の
両端部に嫁合する凸部39,39′を有する絶縁物の蓋
体38を絶縁物片の外面に沿って接着して行なう。他の
実施例としては第5図に示すように、放熱用金属体にス
タッド31を用い、接地を金属帯35,35′にて行っ
ている。
The details of the present invention will be explained below with reference to FIG. 4 showing one embodiment thereof. That is, a heat dissipating insulating plate 32 having a width sufficient for mounting a semiconductor chip and a relatively thin thickness is adhered onto the heat dissipating metal plate 31, and is thicker than this insulating plate 32 and has side surfaces sandwiching it. an insulator piece 36 in contact with
36' is glued onto the heat dissipation metal plate 31, and the input/output metal band 3
3 and 34 are glued to the top surface of the insulator piece. For grounding, for example, a metal film 35 formed by metallization on both ends of the heat dissipation insulating plate.
, 35'. The bonding point for the semiconductor chip is selected approximately at the center of the upper surface of the heat dissipation insulating plate 32, and either the input/output metal strip or the ground metal film is extended up to this point.
In the illustrated example, the output metal band 34 is extended. This extension portion and the heat dissipation insulating plate 32 must be bonded well thermally. The semiconductor chip is isolated from the outside atmosphere by using an insulating lid 38 having protrusions 39, 39' that engage both ends of a recess 37 formed by an insulating plate 32 and insulating pieces 36, 36'. Glue along the outer surface of the insulator piece. In another embodiment, as shown in FIG. 5, a stud 31 is used as the heat dissipating metal body, and grounding is performed using metal bands 35, 35'.

上記のように構成した第4図、第5図の実施例において
は、放熱用絶縁板はその両側面にて絶縁物片に接してい
るので、半導体チップからの熱は絶縁板の底面だけでな
く、その側面からも補助的に放散されその放熱効果は極
めて大である。
In the embodiments shown in FIGS. 4 and 5 constructed as described above, the heat dissipation insulating plate is in contact with the insulator piece on both sides, so the heat from the semiconductor chip is absorbed only from the bottom of the insulating plate. In addition, the heat is radiated supplementally from the sides, and the heat radiation effect is extremely large.

一例として放熱用絶縁板として厚さ0.2柳のEFG法
によって作ったサファイア板を、両側の厚い絶縁物片と
して厚さ1.5側のアルミナセラミック片を用いたもの
で、厚さ1.4脚のべリリアセラミック板を用いた第1
図の構成の従来例と比して熱的および高周波的にほぼ同
等の性能を示すことが認められた。本発明の外囲器の変
形例として第6図に示すように一方、例えば入力金属帯
33を載せる絶縁物片36に凹所36Aを形成し、ここ
に沿って金属帯33を曲折し、この部分に紬線を接続し
てその長さを短かくすることができる。
As an example, a sapphire plate made by the EFG method with a thickness of 0.2 willow is used as a heat dissipation insulating plate, and alumina ceramic pieces with a thickness of 1.5 are used as thick insulating pieces on both sides. The first using four beryllia ceramic plates.
It was found that the device exhibited almost the same thermal and high frequency performance as the conventional example with the configuration shown in the figure. As a modified example of the envelope of the present invention, as shown in FIG. You can shorten the length by connecting a pongee line to the part.

また第7図に示すように放熱用絶縁板32をその両側の
絶縁物片36,36′より短か〈することもできる。
Further, as shown in FIG. 7, the heat dissipating insulating plate 32 can be made shorter than the insulating pieces 36, 36' on both sides thereof.

さらに半導体チップをまたいで橋状に接地用金属片を配
置し、これに接地用紬線を接続するようにしてもよい。
なお外囲器の製作を容易にするために、例えば放熱用金
属体に上記の絶縁板、絶縁物片、接地用金属片の鉄合す
るような凹部を形成して粗立てることもできる。
Furthermore, a grounding metal piece may be arranged in a bridge shape across the semiconductor chip, and a grounding pongee wire may be connected to this.
In order to facilitate the manufacture of the envelope, it is possible to roughen the heat dissipating metal body by forming, for example, a recess into which the above-mentioned insulating plate, insulator piece, and grounding metal piece fit together.

上言己より明らかなように本発明の半導体外囲器では、
半導体チップを戴置する放熱用絶縁薄板はその側面がア
ルミナ等のセラミック絶縁片と接し、この絶縁片を通じ
ても熱放散が行なわれるので、半導体チップで発生した
熱の迅速な放熱を行なうことができる。
As is clear from the above, in the semiconductor envelope of the present invention,
The side surface of the thin heat dissipating insulating plate on which the semiconductor chip is mounted is in contact with a ceramic insulating piece made of alumina, etc., and heat is dissipated through this insulating piece as well, so the heat generated by the semiconductor chip can be rapidly dissipated. .

従って放熱用絶縁板として熱伝導性の比較的低い例えば
サファイア薄板も使用することができるので、その加工
性および量産性の優れている点で外囲器の低価格化を可
能にするものである。
Therefore, a thin sapphire plate with relatively low thermal conductivity, such as a thin sapphire plate, can be used as a heat-dissipating insulating plate, which makes it possible to lower the price of the envelope due to its excellent workability and mass production. .

【図面の簡単な説明】[Brief explanation of the drawing]

0 第1図ないし第3図は従来の半導体外囲器の斜視図
、第4図ないし第7図は本発明の半導体外園器の斜視図
である。 1,11,21,31・・・放熱用金属体、2,12,
22,32・・・放熱用絶縁板、3,13,23,33
・・・入力金属帯、4,14,24,34・・・出力金
属帯、5,5′,15,15′25,25′,35,3
5′…接地用金属、6,26,38…蓋体、16…封止
モールド、7…半導体チップ、8,9,9′,29・・
・接続用細線、27・・・電極支持用絶縁物環、36,
36′・・・電極支持用絶縁物片、36A・・・凹所、
37・・・凹部、39,39′・・・凸部。 第1図 第2図 第3図 第4図 第5図 第6図 第7図
0 FIGS. 1 to 3 are perspective views of conventional semiconductor envelopes, and FIGS. 4 to 7 are perspective views of semiconductor envelopes of the present invention. 1, 11, 21, 31...metal body for heat radiation, 2, 12,
22, 32... Heat dissipation insulating plate, 3, 13, 23, 33
... Input metal band, 4, 14, 24, 34 ... Output metal band, 5, 5', 15, 15' 25, 25', 35, 3
5'...Grounding metal, 6, 26, 38...Lid, 16...Sealing mold, 7...Semiconductor chip, 8, 9, 9', 29...
- Thin wire for connection, 27... Insulator ring for electrode support, 36,
36'... Insulator piece for electrode support, 36A... Recess,
37... Concave portion, 39, 39'... Convex portion. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 1 放熱用金属体と、これに接着されて半導体チツプを
載置させるための放熱用絶縁板と、この絶縁板よりも厚
く、その側面に接して上記金属体に接着された絶縁性電
極支持片とから成る半導体チツプ支持部と、上記半導体
チツプを外雰囲気から隔離するように上記支持部に接着
される蓋体とから構成される半導体外囲器。
1. A heat dissipating metal body, a heat dissipating insulating plate bonded to the heat dissipating insulating plate on which a semiconductor chip is placed, and an insulating electrode support piece that is thicker than the insulating plate and bonded to the metal body in contact with the side surface of the insulating plate. A semiconductor envelope comprising: a semiconductor chip support portion; and a lid member adhered to the support portion so as to isolate the semiconductor chip from the outside atmosphere.
JP8716976A 1976-07-23 1976-07-23 semiconductor envelope Expired JPS6032977B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8716976A JPS6032977B2 (en) 1976-07-23 1976-07-23 semiconductor envelope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8716976A JPS6032977B2 (en) 1976-07-23 1976-07-23 semiconductor envelope

Publications (2)

Publication Number Publication Date
JPS5313360A JPS5313360A (en) 1978-02-06
JPS6032977B2 true JPS6032977B2 (en) 1985-07-31

Family

ID=13907475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8716976A Expired JPS6032977B2 (en) 1976-07-23 1976-07-23 semiconductor envelope

Country Status (1)

Country Link
JP (1) JPS6032977B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60105240A (en) * 1983-11-11 1985-06-10 Sumitomo Electric Ind Ltd Package for semiconductor element

Also Published As

Publication number Publication date
JPS5313360A (en) 1978-02-06

Similar Documents

Publication Publication Date Title
US4172261A (en) Semiconductor device having a highly air-tight package
JPS63205935A (en) Resin-sealed type semiconductor device equipped with heat sink
KR960706194A (en) A LEAD FRAME HAVING LAYERED CONDUCTIVE PLANES
JPS59130449A (en) Insulation type semiconductor element
US4314270A (en) Hybrid thick film integrated circuit heat dissipating and grounding assembly
EP0304058B1 (en) Mounting of a transistor device on a lead frame with a ceramic plate
US3611059A (en) Transistor assembly
JPS6032977B2 (en) semiconductor envelope
JP2905609B2 (en) Resin-sealed semiconductor device
JPH0645504A (en) Semiconductor device
JPS639664B2 (en)
JPS6146975B2 (en)
JP2828553B2 (en) Semiconductor device
JPS5810360Y2 (en) Packages for semiconductor devices
JPH0758746B2 (en) Resin-sealed semiconductor device
JPS5810840A (en) Semiconductor device
JPS5917273A (en) Resin sealed semiconductor device
JPS6056298B2 (en) semiconductor equipment
JPS6023974Y2 (en) semiconductor equipment
JPH0434827B2 (en)
JPH03101256A (en) Semiconductor device
JPS588582B2 (en) Coaxial package for transistors
JP2831219B2 (en) Semiconductor device
JPH0561780B2 (en)
JPH0697359A (en) LSI chip mounting structure