JPS639664B2 - - Google Patents
Info
- Publication number
- JPS639664B2 JPS639664B2 JP56042208A JP4220881A JPS639664B2 JP S639664 B2 JPS639664 B2 JP S639664B2 JP 56042208 A JP56042208 A JP 56042208A JP 4220881 A JP4220881 A JP 4220881A JP S639664 B2 JPS639664 B2 JP S639664B2
- Authority
- JP
- Japan
- Prior art keywords
- gaasfet
- metal
- electrode
- semiconductor device
- metal base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/10—Arrangements for heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/737—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に半導体素子か
ら発生する熱の放散性が改善された素子収容容量
(パツケージ)の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a structure of an element storage capacity (package) with improved dissipation of heat generated from a semiconductor element.
半導体装置の一つであるガリウム・砒素電界効
果型トランジスタ(GaAsFET)は、半導体材料
としてシリコンSiを用いた半導体装置に比較し
て、より高周波域において使用することができる
という特長を有している。しかしながら、基体材
料であるガリウム・砒素がシリコンに比較して熱
伝導度が低く(熱抵抗が高く)、大電力,高出力
を扱うことが困難である。すなわち、シリコンの
熱伝導度が1.5〔W/cm・℃〕であるのに対して、
ガリウム・砒素の熱伝導度は0.4〔W/cm・℃〕程
である。 Gallium-arsenide field-effect transistors (GaAsFETs), which are a type of semiconductor device, have the advantage of being able to be used in higher frequency ranges than semiconductor devices that use silicon Si as the semiconductor material. . However, the base material, gallium and arsenic, has lower thermal conductivity (higher thermal resistance) than silicon, making it difficult to handle large amounts of power and output. In other words, while the thermal conductivity of silicon is 1.5 [W/cm・℃],
The thermal conductivity of gallium and arsenic is about 0.4 [W/cm・℃].
このため、かかるGaAsFETにおける熱放散性
を改善して当該GaAsFETの大電力化,高出力化
を図るための手段として、例えば第1図に示され
る素子固着構造の他に、例えば第2図に示される
ようないわゆるアツプサイドダウンマウント構造
が提案されている。 Therefore, in addition to the device fixing structure shown in FIG. 1, for example, as a means for improving the heat dissipation property of the GaAsFET and increasing the power and output of the GaAsFET, as shown in FIG. A so-called upside down mount structure has been proposed.
第1図において、11はGaAsFET素子、12
は前記GaAsFET素子11が搭載固着される無酸
素銅製金属基体である。当該金属基体12は放熱
体並びに前記GaAsFETのソース電極を構成す
る。すなわち、GaAsFET11のソース電極は通
常のリード線あるいは当該GaAsFET素子11の
側面に延在される金属化層によつて当該金属基体
11へ電気的に接続される。また、13は前記金
属基体12上に前記GaAsFET素子11を囲む如
く配設されたセラミツク製絶縁体枠であり、その
表面には前記GaAsFET素子11のゲート電極及
びドレイン電極から導出されたリード線14A,
14Bが接続されるメタライズ層15A,15B
が配設される。また、16は前記絶縁体枠13上
に配設された気密封止用セラミツク製絶縁体枠で
あり、その頂面には金属製あるいはセラミツク製
の蓋17が配設されて前記GaAsFET素子11が
気密封止される。更に、18A,18Bは前記絶
縁体枠16の外側において、前記メタライズ層1
5A,15Bに接続固着された外部接続端子であ
る。 In Figure 1, 11 is a GaAsFET element, 12
is a metal base made of oxygen-free copper on which the GaAsFET element 11 is mounted and fixed. The metal base 12 constitutes a heat sink and a source electrode of the GaAsFET. That is, the source electrode of the GaAsFET 11 is electrically connected to the metal substrate 11 by a conventional lead wire or a metallization layer extending on the sides of the GaAsFET device 11. Reference numeral 13 denotes a ceramic insulator frame disposed on the metal base 12 so as to surround the GaAsFET element 11, and on its surface are lead wires 14A led out from the gate electrode and drain electrode of the GaAsFET element 11. ,
Metallized layers 15A and 15B to which 14B is connected
will be placed. Further, 16 is a ceramic insulator frame for airtight sealing disposed on the insulator frame 13, and a lid 17 made of metal or ceramic is disposed on the top surface of the insulator frame 16 to cover the GaAsFET element 11. Hermetically sealed. Furthermore, 18A and 18B are located outside the insulator frame 16, and are connected to the metallized layer 1.
These are external connection terminals connected and fixed to 5A and 15B.
このような構造においては、GaAsFET素子1
1の表面の活性領域から発した熱は、当該
GaAsFET素子の基体を通して金属基体12へ伝
導される。しかしながら、前述の如く、GaAs基
体は熱伝導性が低いために、当該GaAsFETの大
電力化高出力化は困難である。 In such a structure, GaAsFET element 1
The heat emitted from the active area on the surface of
It is conducted to the metal substrate 12 through the substrate of the GaAsFET device. However, as described above, since the GaAs substrate has low thermal conductivity, it is difficult to increase the power and output of the GaAsFET.
このため、第2図に示される如き素子搭載,固
着構造が提案されている。同図において、前記第
1図に示される部位と同一箇所には同一符号を付
している。 For this reason, an element mounting and fixing structure as shown in FIG. 2 has been proposed. In this figure, the same parts as those shown in FIG. 1 are given the same reference numerals.
第2図に示される構造にあつては、GaAsFET
素子11の例えばソース電極が金の厚メツキ体2
1から構成され、当該GaAsFET素子11は前記
第1図に示される構成とは表裏を逆にして、前記
金の厚メツキ電極21が金属基体12へ固着され
る。 In the structure shown in Figure 2, the GaAsFET
For example, the source electrode of the element 11 is a thick plated body 2 of gold.
1, the GaAsFET element 11 is reversed from the structure shown in FIG. 1, and the thick gold plated electrode 21 is fixed to the metal base 12.
このような構造によれば、GaAsFET素子11
の活性領域から発生した熱は金の厚メツキ電極2
1を通して放熱基体11へすみやかに伝達され
る。しかしながら、かかる構造にあつては金の厚
メツキ電極21の断面積を大きくすることに限度
があり、十分な放熱効果は期待できない。 According to such a structure, the GaAsFET element 11
The heat generated from the active region of the thick gold plated electrode 2
1 to the heat dissipation base 11. However, in such a structure, there is a limit to increasing the cross-sectional area of the thick gold plated electrode 21, and a sufficient heat dissipation effect cannot be expected.
本発明はこのような従来の構造に代えて、より
効果的な放熱を行なうことができる構造を有する
半導体装置を提供しようとするものである。 The present invention aims to provide a semiconductor device having a structure capable of more effective heat dissipation in place of such a conventional structure.
このため、本発明によれば金属基体と、前記金
属基体上に固着された半導体素子と、前記金属基
体上に配設され前記半導体素子を囲む前記絶縁物
部材と、前記絶縁物部材上に配置された蓋部材と
を備えた半導体装置において、前記半導体素子の
所望の電極が当該半導体素子の活性領域上に突出
して形成され、前記突出形成された電極に接して
導電性薄膜が配設され、前記導電性薄膜と前記蓋
部材との間に導電性部材が充填されてなる半導体
装置が提供される。 Therefore, according to the present invention, there is provided a metal base, a semiconductor element fixed on the metal base, the insulator member disposed on the metal base and surrounding the semiconductor element, and the insulator member disposed on the insulator member. In the semiconductor device, a desired electrode of the semiconductor element is formed to protrude above an active region of the semiconductor element, and a conductive thin film is disposed in contact with the protruding electrode, A semiconductor device is provided in which a conductive member is filled between the conductive thin film and the lid member.
以下、本発明を実施例をもつて詳細に説明す
る。第3図は本発明による半導体装置の一実施例
の構成を示す。 Hereinafter, the present invention will be explained in detail using examples. FIG. 3 shows the structure of an embodiment of a semiconductor device according to the present invention.
第3図において、101はGaAsFET素子、1
02は前記GaAsFET素子101が搭載固着され
る無酸素銅製金属基体である。当該金属基体10
2は放熱体を構成する。そして、GaAsFET素子
101のソース電極をリード線あるいは当該
GaAsFET素子101の側面に延在される金属化
層によつて接続すれば、当該金属基体102は
GaAsFET素子101のソース電極を構成する。 In Fig. 3, 101 is a GaAsFET element, 1
02 is a metal base made of oxygen-free copper on which the GaAsFET element 101 is mounted and fixed. The metal base 10
2 constitutes a heat sink. Then, connect the source electrode of the GaAsFET element 101 to the lead wire or
If connected by a metallization layer extending on the sides of the GaAsFET device 101, the metal substrate 102
It constitutes the source electrode of the GaAsFET element 101.
また、103は前記金属基体102上に前記
GaAsFET素子101を囲むごとく配設されたセ
ラミツク製絶縁体枠であり、その表面には前記
GaAsFET素子101のゲート電極及びドレイン
電極から導出されたリード線104A,104B
が接続されるメタライズ層105A,105Bが
配設される。 Moreover, 103 is the above-mentioned on the metal base 102.
This is a ceramic insulator frame arranged to surround the GaAsFET element 101, and its surface has the above-mentioned
Lead wires 104A and 104B derived from the gate electrode and drain electrode of the GaAsFET element 101
Metalized layers 105A and 105B to which are connected are provided.
また、106は前記絶縁体枠13上に配設され
た気密封止用セラミツク製絶縁体枠であり、その
頂面には金属性例えば銅製の蓋107が配設され
て前記GaAsFET素子101が気密封止される。 Further, 106 is a ceramic insulator frame for airtight sealing arranged on the insulator frame 13, and a lid 107 made of metal, for example, copper, is arranged on the top surface of the insulator frame 106, so that the GaAsFET element 101 can be air-tightly sealed. sealed.
更に、108A,108Bは前記絶縁枠体10
6の外側において、前記メタライズ層105A,
105Bに接続固着されたコバール製外部接続端
子である。 Furthermore, 108A and 108B are the insulating frame 10.
6, the metallized layer 105A,
This is an external connection terminal made of Kovar that is connected and fixed to 105B.
本発明にあつては、前記GaAsFET素子101
のソース電極が金の厚メツキ体109から構成さ
れる。また、前記気密封止用絶縁体枠106の頂
部近傍から前記ソース電極109に接して金等の
厚さ20〜100〔μm〕の金属薄膜110が配設され
る。当該金属薄膜110はソース電極109に熱
圧着によつて接続され、且つ、その周縁部は封止
用絶縁体枠106に設けられたメタライズ層(図
示せず)に熱圧着されて固定される。更に、本発
明にあつては、前記金属薄膜110と前記蓋10
7との間の空間に、例えば金属Ag粒子が混入さ
れた導電性エポキシ樹脂等熱伝導性の良い樹脂1
11が充填される。 In the present invention, the GaAsFET element 101
The source electrode is composed of a thick gold plated body 109. Further, a metal thin film 110 made of gold or the like having a thickness of 20 to 100 [μm] is disposed in contact with the source electrode 109 from near the top of the hermetic sealing insulator frame 106 . The metal thin film 110 is connected to the source electrode 109 by thermocompression bonding, and its peripheral portion is thermocompression bonded and fixed to a metallized layer (not shown) provided on the sealing insulator frame 106. Furthermore, in the present invention, the metal thin film 110 and the lid 10
In the space between 7 and 7, a resin 1 with good thermal conductivity, such as a conductive epoxy resin mixed with metal Ag particles, is placed.
11 is filled.
ここで、当該半導体装置の組立てに当つては、
前記蓋107の取り付けに先行して、金属薄膜1
10の配設,樹脂111の充填がなされることは
当然である。 Here, when assembling the semiconductor device,
Prior to attaching the lid 107, the metal thin film 1 is
10 and the resin 111 is filled.
更に、本発明にあつては、前記蓋107には外
部取り付け用スタツド112が配設されてなり、
当該スタツド112は放熱体113に設けられた
貫通孔114に挿入され、更に、ナツト115に
よつて当該放熱体113に機械的に固定され得る
構成とされる。 Furthermore, in the present invention, the lid 107 is provided with an external mounting stud 112,
The stud 112 is inserted into a through hole 114 provided in the heat sink 113 and is further configured to be mechanically fixed to the heat sink 113 by a nut 115.
このような本発明によれば、GaAsFET素子1
01のソース電極は、基体金属基体102へと金
属薄膜110,合成樹脂層111,蓋107を通
してスタツド112へとの2方向へ導出される。 According to the present invention, the GaAsFET element 1
The source electrode 01 is led out in two directions: to the base metal substrate 102, through the metal thin film 110, the synthetic resin layer 111, and the lid 107 to the stud 112.
そして、当該GaAsFET素子101の活性領域
から発生された熱は、当該GaAsFET素子101
の基体を通して金属基体102及び該金属基体1
02が固着される放熱体116へ伝導されるとと
もに厚メツキ電極109,金属薄膜110,樹脂
111,蓋107及びスタツド112を通して放
熱体113へ伝導される。 Then, the heat generated from the active region of the GaAsFET element 101 is transferred to the GaAsFET element 101.
through the base of the metal base 102 and the metal base 1
02 is conducted to the heat sink 116 to which it is fixed, and is also conducted to the heat sink 113 through the thick plating electrode 109, the thin metal film 110, the resin 111, the lid 107, and the stud 112.
したがつて、本発明によれば前記第1図,第2
図に示される構造に比較して、約2倍の熱放散性
を得ることができる。これは、例えば高周波出力
が3〔W〕のGaAsFETにおいて、活性領域の温
度を前記従来構造の場合に比較して50〔℃〕程低
下させることが可能となるものであり、当該
GaAsFET装置の高出力化並びに高信頼性化に極
めて有効である。 Therefore, according to the present invention, the above-mentioned FIGS.
Approximately twice the heat dissipation performance can be obtained compared to the structure shown in the figure. For example, in a GaAsFET with a high frequency output of 3 [W], this makes it possible to lower the temperature of the active region by about 50 [°C] compared to the conventional structure.
It is extremely effective in increasing the output and reliability of GaAsFET devices.
なお、本発明は前記実施例に限定されるもので
はなく、接地電極として前記ソース電極以外の電
極が適用される場合には、かかる接地電極上に厚
メツキ電極を形成すればよい。 It should be noted that the present invention is not limited to the above embodiments, and if an electrode other than the source electrode is used as the ground electrode, a thick plating electrode may be formed on the ground electrode.
また、前記金属薄膜に代えて、表面が金属化処
理された合成樹脂膜を用いることもできる。かか
る合成樹脂膜表面の金属化層と前記蓋との電気的
接続は当該合成樹脂膜の絶縁物枠体103への固
着部メタライズ層と樹脂111を通じて行なうこ
とができる。 Furthermore, instead of the metal thin film, a synthetic resin film whose surface has been metallized can also be used. Electrical connection between the metallized layer on the surface of the synthetic resin film and the lid can be made through the resin 111 and the metallized layer of the synthetic resin film fixed to the insulator frame 103 .
また、樹脂111に代えて半田等の低融点金属
を充填してもよい。 Further, instead of the resin 111, a low melting point metal such as solder may be filled.
更に、前記放熱体113と116とは一体のも
のであつてもよい。放熱体113と116とが一
体物であれば接地電位の一定化を図ることができ
る。 Furthermore, the heat sinks 113 and 116 may be integrated. If the heat sinks 113 and 116 are integrated, the ground potential can be made constant.
第1図及び第2図は、従来の半導体装置の構造
を示す断面図である。第3図は本発明による半導
体装置の構造を示す断面図である。
図において、11,101……半導体素子、1
2,102……金属基体、13,103……絶縁
物枠体、16,106……封止用絶縁物枠体、1
7,107……蓋、21,109……金属厚メツ
キ層、110……導電性薄膜、111……樹脂、
112……スタツド、である。
1 and 2 are cross-sectional views showing the structure of a conventional semiconductor device. FIG. 3 is a sectional view showing the structure of a semiconductor device according to the present invention. In the figure, 11,101...semiconductor element, 1
2,102...Metal base, 13,103...Insulator frame, 16,106...Insulator frame for sealing, 1
7,107... Lid, 21,109... Metal thick plating layer, 110... Conductive thin film, 111... Resin,
112...Stud.
Claims (1)
導体素子と、前記金属基体上に配設され前記半導
体素子を囲む絶縁物部材と、前記絶縁物部材上に
配置された蓋部材とを備えた半導体装置におい
て、前記半導体素子の所望の電極が当該半導体素
子の活性領域上に突出して形成され、前記突出形
成された電極に接して導電性薄膜が配設され、前
記導電性薄膜と前記蓋部材との間に導電性部材が
充填されてなることを特徴とする半導体装置。1 comprising a metal base, a semiconductor element fixed on the metal base, an insulator member disposed on the metal base and surrounding the semiconductor element, and a lid member disposed on the insulator member. In the semiconductor device, a desired electrode of the semiconductor element is formed to protrude above an active region of the semiconductor element, a conductive thin film is disposed in contact with the protruding electrode, and the conductive thin film and the lid member are disposed in contact with the protruding electrode. A semiconductor device characterized in that a conductive member is filled between the semiconductor device and the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56042208A JPS57157550A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56042208A JPS57157550A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57157550A JPS57157550A (en) | 1982-09-29 |
| JPS639664B2 true JPS639664B2 (en) | 1988-03-01 |
Family
ID=12629594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56042208A Granted JPS57157550A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57157550A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144982U (en) * | 1988-03-28 | 1989-10-05 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61114659A (en) * | 1984-11-09 | 1986-06-02 | Hitachi Ltd | Video output circuit |
| JPS61125156A (en) * | 1984-11-22 | 1986-06-12 | Nec Corp | Semiconductor device |
| CN105051898B (en) * | 2013-08-23 | 2018-01-16 | 富士电机株式会社 | Semiconductor device |
| JP6108026B1 (en) * | 2016-12-16 | 2017-04-05 | 富士電機株式会社 | Pressure contact type semiconductor module |
-
1981
- 1981-03-23 JP JP56042208A patent/JPS57157550A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144982U (en) * | 1988-03-28 | 1989-10-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57157550A (en) | 1982-09-29 |
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