JPS6032982B2 - Manufacturing method of semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a method for manufacturing a semiconductor memory which can easily be highly integrated, has small variations in element characteristics, and has a simple structure.

{2l Prior Art As semiconductor memories become more highly integrated, a structure is being adopted in which the electrodes on the storage area and the electrodes on the transfer area are at least partially overlapped.

Therefore, when processing each electrode, variations occur in the channel length of the transfer region due to alignment accuracy. Furthermore, as the electrodes are stacked in multiple layers, new problems arise in processing, such as a significant increase in the level difference and the occurrence of disconnections in the wiring. Further, a technique related to etching of a stabilizing film is disclosed in Japanese Patent Publication No. 44-2353.

(3' Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks. It eliminates channel length variations in the transfer region, eliminates multi-layered electrode wiring, and provides a semiconductor memory that can be highly integrated. The purpose is to provide a manufacturing method.■
General Description of the Invention In the method of manufacturing a semiconductor memory provided by the present invention, there are two particular techniques that make the present invention possible.

One is to form the transfer region by side etching technology. Another technique is to perform wet thermal oxidation at a relatively low temperature to simultaneously form interlayer insulating films between storage areas, transfer areas, data line areas, and word lines, each with a different thickness. . As a means to enable the above-mentioned side etching, since the upper part of the electrode on the storage area is not removed by etching, it is necessary to cover the upper part by 4 times the etching rate compared to the above-mentioned electrode member. There is.

Polycrystalline silicon is used as the electrode member, and CVD (Chemica Vapor Deposition) is used as the material with a low etching rate.
A silicon oxide film, a silicon nitride film, or the like (orDeposition) film is effective. Furthermore, it is effective to use plasma etching technology for etching. A comparatively low-temperature wet thermal oxidation method can be used as a means for forming the interlayer insulating film to have different thicknesses in different regions.

At this time, it is effective that the storage electrode is made of polycrystalline silicon doped with impurities at a high concentration, and the data line region is formed by being doped with an impurity of a conductivity type opposite to that of the substrate at a high concentration. In low-temperature wet thermal oxidation, the oxidation rate has extremely significant impurity concentration dependence, and the interlayer oxide films formed on different regions can be formed to have different thicknesses. Note that since the oxide film on the transfer region is formed by low-temperature wet thermal oxidation, a problem may occur in terms of stability of device operation. As a countermeasure, it is effective to remove the low-temperature wet thermal oxide film only on the transfer region, and then form a high-quality insulating film on the transfer region by high-temperature dry thermal oxidation. (2) Examples Hereinafter, the present invention will be explained in detail with reference to examples.

In the following description, a p-type semiconductor wafer will be described, but it goes without saying that an n-type semiconductor wafer may also be used.
It should also be noted that various modifications may be made without departing from the spirit of the invention. FIG. 1 is a plan view showing a semiconductor memory formed by the manufacturing method of the present invention.

1 is a storage area, 2 is a data line area, 3 is an electrode covering the storage area, 4 is a transfer area, and the shaded area is an area where electrode 3 is removed by side etching, 5
indicates a word line.

FIG. 2 shows a cross section taken along line AA' in FIG.

6 is a semiconductor wafer with a p-type (100) plane and a 10Q arc, 7
-1, 7 and 2 are field oxide films with a thickness of 1 mm thick that form isolation and data line regions, respectively; 11 is an oxide film with a thickness of 5 mm thick in the storage area; and 3 is a thickness that covers the storage area. 13-1 and 13-2 are data line regions heavily doped with impurity arsenic to a depth of 0.4 m, 12 Reference numeral 5 indicates a channel portion where information charges are transferred in and out in the transfer region, and 5 indicates a word line, which is made of A material.

Further, 8, 9 and 10-1, 10-2 indicate interlayer oxide films between the word line 5 and the channel portion 12, the polycrystalline silicon 3, and the data lines 13--, 13-2, respectively.
The method of manufacturing a semiconductor memory provided by the present invention will be described below with reference to FIGS. 3 and 2.

FIG. 3a shows field oxide films 7-1 and 7-2 formed on a semiconductor wafer 6 by selective oxidation for 100,000 hours and 6 hours of wet thermal oxidation.

This shows up to the point where an oxide film 11 is formed by dry thermal oxidation of 0.0 and 5.

In Fig. 3b, after polycrystalline silicon 3 is formed on the entire surface by CVD to a thickness of 0.42 m, PO
After doping impurity into polycrystalline silicon 3 at a high concentration for 30 minutes at 1000 000 in an atmosphere, the polycrystalline silicon 3 is made into a 10 m thick polycrystalline silicon by thermal oxidation using a rice bran method at 750 qo, 6 mm. After forming the thermal oxide film 14, a thickness of 2
After forming a silicon nitride film 15 with a thickness of 0 mm by the CVD method, a silicon nitride film 15 with a thickness of
5. Process the oxide film 14 and polycrystalline silicon 3, and remove the silicon nitride film 15 and field oxide film 7-1 after this processing.
7-2 are used as masks to form word line regions 13-1 and 13-2 by ion implantation.

At this time, in the ion implantation, arsenic was doped by 1×1 and 6-2 at an implantation energy of 150 keV. FIG. 3c shows the state where the polycrystalline silicon 3 is removed from the transfer region 12 by plasma etching technology after a photoresist film 16 is subsequently applied and a side etched portion is opened.

4d shows the state where the photoresist film 16, silicon nitride film 15, oxide film 14, and oxide film 11 on the transfer region 12 and data line regions 13-1 and 13-2 have been removed. .

The following steps will be explained using FIG. Thermal oxidation is performed for 6 hours in a humid atmosphere of 750 oo, and an oxide film 8 with a thickness of 5 mm is formed on the transfer region 12, and an oxide film 8 with a thickness of 36 mm is formed on the polycrystalline silicon 3.
oxide film 9 and data line regions 13-1 and 1
After forming oxide films 10-1 and 10-2 with a thickness of 24 m on each layer 3-2, a word line 5 was formed with a thickness of 80 m by the A-based evaporation method.

It is also possible to use polycrystalline silicon doped with a large amount of impurities to form the word line. However, at this time, the resistance becomes higher than that of the metal material, so the memory access time becomes longer. However, in order to prevent this increase in resistance when polycrystalline silicon is used for the word line, it is effective to form the word line by overlapping polycrystalline silicon and a metal material such as A. Alternatively, in order to prevent the word line from increasing in resistance, it is also possible to form polycrystalline silicon over the transfer region and electrically connect it to the word line formed in sleeve A through a contact hole. FIG. 4 shows the relationship between the oxide film thickness and oxidation time in a wet oxidation atmosphere of 75,000 mm. In Fig. 4, B is the semiconductor wafer, C is the surface of the semiconductor wafer when arsenic is implanted at a depth of 1 x 1 6 cm-2, and D is the surface of the semiconductor wafer when the impurity phosphorus is doped at a high concentration. It shows the relationship between oxide film thickness and oxidation time when crystalline silicon is oxidized. Note that as a method for removing polycrystalline silicon on the transfer region, in addition to side etching, it is also possible to apply a photoresist that closes only the etched portion and use a normal etching speed.

At that time, the silicon nitride film 15 required for the side etching process is not required, and the process is simplified, but the channel length that determines the transfer region will vary by the mask alignment margin, and the channel length will be The disadvantage is that it cannot be decided voluntarily. (6) Summary As explained above, according to the present invention, (i) The channel length of the transfer region is determined by the side etching, and when a large number of semiconductor memories are two-dimensionally arranged, their variation is reduced. The area of the semiconductor memory unit cell is reduced by one-third from 1.5 m of the conventional two-layer poly-Si gate structure to 0.5 m, and {ii) The area of the structure is reduced from 160 mm to 144 mm by removing the mask alignment margin, and the unit cell area is reduced by 10% compared to the conventional two-layer poly-Si gate structure. Since then, a single-layer poly-Si gate structure has been realized, preventing the formation of multiple layers of electrode wiring, eliminating the need to form contact holes between each wiring, and greatly improving the stability and reliability of highly integrated semiconductor memories. improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor memory provided by the manufacturing method of the present invention, FIG. 2 is a cross-sectional view of the semiconductor memory, and FIGS.
, c and d are cross-sectional views showing the method of manufacturing a semiconductor memory of the present invention, and FIG. 4 is a diagram showing the relationship between oxide film thickness and oxidation time during low-temperature wet oxidation. ※/Illustrated brother 2 ※ 3 Izu 4

Claims (1)

[Claims] 1. A storage area for accumulating information charges in a predetermined area of a semiconductor wafer of one conductivity type, a data line area for reading out the information charges, and the information charges sandwiched between the storage area and the data line area. In a method for manufacturing a semiconductor memory, the channel length of the transfer area is set in a self-aligned manner in a method for manufacturing a semiconductor memory, in which a transfer area for inputting and outputting information charges and a word line for controlling inputting and outputting of the information charges are provided so as to pass over the transfer area. In order to determine the data, an electrode member on the storage area is formed up to the transfer area, and then a different type of member having a lower etching rate than the electrode member is formed on the electrode member, and the data is A method of manufacturing a semiconductor memory, comprising implanting impurities of a conductivity type opposite to that of the semiconductor wafer into the line region, and then removing the electrode member on the transfer region by side etching.