JPS6035822B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a structure in which a semiconductor substrate and a supporting electrode are bonded via a bond.

Generally, in order to conduct electricity and reinforce the Sj or Ge semiconductor substrate, W, Mo, or the like having a similar thermal expansion coefficient is used as a supporting electrode, and both have a pressure-welded or brazed structure.

It has a brazing structure, and soft solder is used as the brazing material for small-capacity semiconductor devices, and hard solder is used for large-capacity semiconductor devices. This is closely related to thermal fatigue during energized use. Pb-Sn, Pb-Ag-S are used for soft solder with low thermal fatigue strength.
There are n, etc. On the other hand, pure AI, AI-Si or AI-G
e, AI-Sb, etc. belong to hard solders and have excellent electrical and thermal conductivity, as well as excellent properties for etching operations essential to semiconductor manufacturing processes. N solder is suitable as a solder and provides satisfactory results when only a single p-type conductive region is exposed at the surface of the semiconductor body. However, when bonding a support electrode to a semiconductor body with an exposed surface of an n-type conductive region, disadvantageous results occur. That is, to explain this with respect to a Si semiconductor substrate, in the N brazing operation between the semiconductor substrate and the supporting electrode, a part of the surface of the n-type conductive region melts into the AI solder. The melted Si contains trivalent AI and recrystallizes on the surface of the n-type conductive region during the cooling process to form a regrown layer of p-type conductivity. A region that is inverted to p-type is generated where it should be n-type, resulting in a forward voltage drop (F
There is a drawback that the amount of energy (abbreviated as VD) increases. In the past, studies have been conducted on brazing filler metals in which secondary and tertiary elements are added to the river with the aim of suppressing the formation of a regrowth layer and reducing FVD, but sufficient effects have not been achieved. .

Therefore, while proceeding with research to eliminate the above drawbacks,
We believe that lowering the brazing temperature is the most effective method. However, lowering the bonding temperature when only N is present will impair the integrity of the bonded area, which in turn may cause cracks to occur due to pressure and an increase in thermal resistance. Therefore, brazing temperature is restricted. Therefore, while considering methods that could be bonded at low temperatures, we found that diffusion bonding using an AI solder on the semiconductor substrate side and a Cu solder on the supporting electrode side would be effective. did. In this structure, the brazing temperature only needs to be 530°C or higher, which is 72°C when using conventional AI or Yamaichi Si alloy brazing.
It can be lowered by about 20,000 compared to 0 to 740 qo. As a result of applying this adhesive structure to semiconductor devices, FVD
was significantly reduced compared to that using AI wax. However, it has become clear that the breakdown voltage tends to deteriorate. This will reduce the reliability of the product. Therefore,
It is important to eliminate the above drawbacks. Therefore, an object of the present invention is to take advantage of a structure in which a semiconductor substrate and a supporting electrode are bonded together at low temperature using a combination of mountains and Cu to reduce FVD.
Another object of the present invention is to provide a semiconductor device without deterioration in breakdown voltage.

Conventionally, in bonding a semiconductor substrate and a support electrode using an AI solder, there has been no evidence of voltage resistance deterioration caused by the AI solder.

The cause of this breakdown voltage deterioration is thought to be due to the presence of Cu. The Cu atoms may diffuse into the semiconductor substrate. The causes of breakdown voltage deterioration are presumed to be a reduction in the spread of the depletion layer due to the diffusion of Cu atoms, and the generation of internal stress due to the diffusion of Cu atoms with a large ionic radius. Therefore,
The present invention was made with consideration to preventing the diffusion of Cu atoms into a semiconductor substrate.As a result, the film surface of one in which a Cu solder is fixed on a supporting electrode and one in which an AI solder is provided on a semiconductor substrate. When heated in a structure in which comrades are in contact, Cu-A
The temperature below the common point according to the binary system phase diagram of I (54800
) was found to be bondable. It was found by cross-sectional analysis using an X-ray microanalyzer that the brazing filler metal part had a ternary system of AI-Cu-Sj. Further C
From the binary system phase diagram of u and Si, the solubility of Cu in Si is 9 x 10-5 atomic % at 800°C, although it is extremely small. For these reasons, direct contact between Cu and the semiconductor substrate should be avoided. Therefore, in the present invention, a metal layer having a high melting point and good adhesion to the semiconductor is provided on the surface of the semiconductor substrate as a barrier metal to prevent Cu atoms from diffusing into the semiconductor substrate.

Examples of the metal film include Cr, Ni, Ti, Mo, W, etc., but Cr and Ni are optimal because they have good adhesion to the Si substrate at low temperatures and are easy to work with.

Furthermore, since the eutectic temperature of the AI-Si alloy solder is lower than that of pure N, the nail solder can be bonded at a low temperature. The present invention will be specifically explained below using examples.

Example 1 FIG. 1 shows an example of the cross-sectional structure of the present invention.

This was produced as follows. A Cr layer 2 and an AI solder 3 are deposited in this order on the surface of the n-type conductive region of a silicon diode wafer 1 having a pnn+ structure. The film thicknesses are about 0.1 and 15 mm, respectively. On the other hand, Cu solder 5 is placed loA on the W supporting electrode 4 which has been degreased and cleaned.
After about 100 m of vapor deposition, a sintering process was performed for 10 minutes in a reducing atmosphere at 700°C. Both were set in a graphite jig so as to have the structure shown in FIG. 1, and heat treated for 30 minutes at 560:00. The atmosphere for the heat treatment is N2.
In addition, 6 in the figure is an M electrode film. The breakdown voltage of the semiconductor device manufactured with such a structure satisfied the nominal breakdown voltage of the diode wafer 1 itself, and no degradation in breakdown voltage was observed.

Further, in the cross-sectional structure observation, no regrowth layer was observed on the surface of the n+ type conductive region. Conventional N-C without Cr layer 2
In the case of u brazing metal, if heat treatment is performed at 530 pm or higher,
Although thin, a regrowth layer was observed on a part of the surface of the n-type conductive region. By providing the Cr layer 2 of the present invention, diffusion of N or Cu into the wafer can be prevented. Further, the evaporated Cr layer 2 and the wafer 1 can be sintered during the brazing operation, and no heat treatment is required after Cr evaporation. Embodiment 2 FIG. 2 shows a cross-sectional structure when the present invention is applied to a glacivation bellet.

The moat 7 has a pressure resistance and is protected by the glass 8, but the heat resistance temperature of the glass 8 is 550 to 560 degrees.
It is. Therefore, instead of the AI solder in Example 1, 20
Using Yamaichi Sj eutectic alloy filler 3 with a thickness of 540GO
A heat treatment was performed for 3 minutes. The Cr layer 2 and the Cu layer 6 are the same as in Example 1. Even in this structure, no deterioration in breakdown voltage was observed. The conventional glaciation pellet 10 and supporting electrode 4 are bonded using Cr-Ni-Ag.
The vapor deposited film and Pb-Ag-Sn solder were combined and bonded together, but the process was complicated and the pressure resistance was low.However, it has been found that the structure of the present invention eliminates these drawbacks. Ta. As described above, in the present invention, since the diffusion of Cu atoms into the semiconductor substrate can be prevented, there is no deterioration in breakdown voltage.

Furthermore, although the present invention is particularly effective for adhering the exposed surface of the n-type conductive region and the supporting electrode, it is useful when warping of the supporting electrode or semiconductor substrate or generation of thermal stress is a problem because the bonding temperature is low. It is valid. Moreover, it can be applied not only to diodes but also to various semiconductor devices such as transistors and thyristors. Further, as shown in FIG. 2, it can also be applied to a p-type region.

[Brief explanation of the drawing]

1 and 2 are sectional views of essential parts of semiconductor devices showing different embodiments of the present invention, respectively. 1... Diode wafer, 2... Cr layer, 3... Mountain wax, 4... Support electrode, 5... Cu wax, 6...
...AI electrode film, 7...Moat, 8...Glass,
10... Gracibasion Berets. Zhu Yiwei Figure 2

Claims (1)

[Claims] 1. In a semiconductor device in which a semiconductor substrate and an electrode supporting the same are bonded by a brazing material, a barrier metal made of a high melting point metal is arranged on the exposed surface of the semiconductor substrate, and a Cu solder is arranged on the side of the supporting electrode. The semiconductor device further comprises an Al or an alloy solder of Al and Si or Ge between the barrier metal and the Cu solder.