JPS6317332B2 - - Google Patents
Info
- Publication number
- JPS6317332B2 JPS6317332B2 JP56147549A JP14754981A JPS6317332B2 JP S6317332 B2 JPS6317332 B2 JP S6317332B2 JP 56147549 A JP56147549 A JP 56147549A JP 14754981 A JP14754981 A JP 14754981A JP S6317332 B2 JPS6317332 B2 JP S6317332B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode metal
- brazing
- deposited
- deposited film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】 この発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
半導体装置の製造方法において、表面にn型拡
散層を有するSi基板と電極金属をロー付するに
は、従来、第1図に示すように行なつていた。第
1図において、まずSi基板1の表面にAl蒸着膜
2を形成した後、さらにその上面にAlと共晶を
作る元素(例えばSi,Ge)よりなる蒸着膜3を
形成する。その後、この蒸着膜3と電極金属4
(例えばMo,W)とを加熱接合させる手段がと
られている。この従来方法を用いて蒸着膜3と電
極金属4との良好な接着を得るためには、加熱接
合温度を少なくとも550℃以上にする必要があつ
た。しかし、加熱接合温度を550℃以上にすると、
Si基板1の表面のSi元素が電極金属とロー材の界
面に析出したり、AlがSi基板1内へ拡散したり
するために、境界層面に反転層(P型による)が
形成され、良好なオーミツク接合が形成されなく
なつてしまう。このため、順方向電圧降下が増大
する欠点があつた。 In a method of manufacturing a semiconductor device, brazing an electrode metal to a Si substrate having an n-type diffusion layer on the surface has conventionally been carried out as shown in FIG. In FIG. 1, first, an Al vapor deposited film 2 is formed on the surface of a Si substrate 1, and then a vapor deposited film 3 made of an element that forms a eutectic with Al (for example, Si, Ge) is further formed on the upper surface. After that, this vapor deposited film 3 and the electrode metal 4
(For example, Mo, W) are heat-bonded. In order to obtain good adhesion between the vapor deposited film 3 and the electrode metal 4 using this conventional method, it was necessary to raise the heating bonding temperature to at least 550° C. or higher. However, when the heating bonding temperature is increased to 550℃ or higher,
Since the Si element on the surface of the Si substrate 1 precipitates at the interface between the electrode metal and the brazing material, and Al diffuses into the Si substrate 1, an inversion layer (due to P type) is formed on the boundary layer surface, resulting in a good condition. A proper ohmic junction is no longer formed. For this reason, there was a drawback that the forward voltage drop increased.
この発明は上記の事情に鑑みてなされたもの
で、Si基板と電極金属にAlとGeを同時に蒸着さ
せるようにしたので、Al−Ge2元素状態図のその
組成における融点以下の温度で加熱接合を可能と
し、良好なオーミツク接合を形成するようにした
半導体装置の製造方法を提供することを目的とす
る。 This invention was made in view of the above circumstances, and since Al and Ge are simultaneously vapor-deposited on the Si substrate and the electrode metal, thermal bonding is possible at a temperature below the melting point of the composition in the Al-Ge2 element phase diagram. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables the formation of a good ohmic junction.
以下図面を参照してこの発明の一実施例を説明
する。 An embodiment of the present invention will be described below with reference to the drawings.
第2図において、11は表面に薄いn型拡散層
を有するSi基板、12はSi基板11にロー付によ
り接着される電極金属である。前記Si基板11と
電極金属12の表面にはAl及びGeを同時に次の
ようにして蒸着させる。これにはAlとGeを別々
に蒸発させてその混合蒸気を用いて蒸着させる
か、あるいはAl−Ge合金を蒸着源として適当な
加速電圧下で電子ビーム蒸着によつて蒸着させる
かの手段がある。このようにしてAl及びGeを同
時にSi基板11と電極金属12の表面に蒸着させ
ると通常の熱処理によつて得られるAl−Ge共晶
よりも微細なGeが分布するようにAlGe蒸着膜1
3a,13bが形成される。このAl−Ge蒸着膜
13a,13bの組成は状態図において、Al初
晶とAl−Ge共晶相とが共存するようなGe5〜
30atm%(原子パーセント)がロー材として適用
できる。なお、熱抵抗及び順方向電圧降下を考慮
すれば、最適組成はGe15〜25atm%であり、こ
の時のロー付温度は不活性ガス雰囲気あるいは水
素ガス雰囲気中若しくは真空中で、450〜550℃で
可能となる。この温度は従来方法に比較して約
100℃近く低い温度でロー付が可能であるを示し
ている。 In FIG. 2, 11 is a Si substrate having a thin n-type diffusion layer on its surface, and 12 is an electrode metal bonded to the Si substrate 11 by brazing. Al and Ge are simultaneously deposited on the surfaces of the Si substrate 11 and the electrode metal 12 in the following manner. This can be done by evaporating Al and Ge separately and using a mixed vapor to deposit them, or by electron beam evaporation using an Al-Ge alloy as a deposition source under an appropriate accelerating voltage. . When Al and Ge are simultaneously deposited on the surfaces of the Si substrate 11 and the electrode metal 12 in this way, the AlGe deposited film 1 is distributed so that finer Ge is distributed than the Al-Ge eutectic obtained by normal heat treatment.
3a and 13b are formed. In the phase diagram, the composition of the Al-Ge deposited films 13a and 13b is such that the Al primary crystal and the Al-Ge eutectic phase coexist.
30 atm% (atomic percent) can be applied as brazing material. In addition, considering thermal resistance and forward voltage drop, the optimum composition is Ge 15 to 25 atm%, and the brazing temperature at this time is 450 to 550℃ in an inert gas atmosphere, hydrogen gas atmosphere, or vacuum. It becomes possible. This temperature is approximately
This shows that brazing is possible at temperatures as low as nearly 100℃.
第3図はB(ボロン)を1014/cm2の濃度で一様
にドープしたP型Si基板の表面よりP(リン)を
表面濃度が1020/cm2で深さが10μ、接合面積が1
cm2となるように拡散し、表面が薄いn型拡散層
(第3図のN+)を形成し、さらに裏面のオーミツ
クコンタクトを取るためにB拡散層1019/cm2で深
さ10μ(第3図のP+)を形成し、アノードW電極
と合金接合したダイオードの実施例である。この
第3図のように形成されたダイオードのn型表面
にAl,Geを2段に蒸着し、600℃でカソードW電
極と加熱接合した従来方法において製造したダイ
オードでは順方向電圧降下(VF)は電流を300A
流すと3〜5Vとなる。しかし、この発明のよう
にAl−Geを同時に蒸着する方法で、(Geが20atm
%)条件が500℃で、Ar雰囲気中で加熱接合して
得られたこの発明のものではVFが1.2〜1.8Vと従
来方法に比較して極めて低い値のものが得られ
た。 Figure 3 shows the surface of a P-type Si substrate uniformly doped with B (boron) at a concentration of 10 14 /cm 2.The surface concentration of P (phosphorous) is 10 20 /cm 2 , the depth is 10μ, and the junction area is is 1
cm 2 , forming a thin n-type diffusion layer (N + in Figure 3) on the surface, and further forming a B diffusion layer 10 19 /cm 2 to a depth of 10μ to make ohmic contact on the back surface. (P + in FIG. 3) is formed and is an example of a diode which is alloy-bonded with the anode W electrode. In a diode manufactured using the conventional method, in which Al and Ge are vapor-deposited in two stages on the n-type surface of the diode formed as shown in Figure 3, and the cathode W electrode is heated and bonded at 600°C, the forward voltage drop (V F ) current is 300A
When flowing, it becomes 3-5V. However, with the method of simultaneous vapor deposition of Al-Ge as in this invention, (Ge is 20atm
%) of the present invention obtained by heating bonding in an Ar atmosphere at 500° C., a V F of 1.2 to 1.8 V, which is extremely low compared to the conventional method, was obtained.
以上述べたように、この発明によれば、Si基板
及び電極金属にAlとGeを同時に蒸着させるよう
にしたので、ロー付温度を低下させることができ
るとともに、ロー付熱処理中に起るAl−Si間の
反応が従来方法と比較して、小さく抑えることが
できる。また順方向電圧降下を小さくでき、さら
にAl−GeのAl%を大きく取ることができるた
め、接触抵抗が低減できる。上記の他に従来のロ
ー付方法に比較して蒸着工程が1回で済むため、
工程が簡略化できる等の利点がある。 As described above, according to the present invention, since Al and Ge are simultaneously vapor-deposited on the Si substrate and the electrode metal, the brazing temperature can be lowered, and the Al- Reactions between Si can be suppressed to a smaller level than in conventional methods. Further, since the forward voltage drop can be reduced and the Al% of Al-Ge can be increased, the contact resistance can be reduced. In addition to the above, compared to conventional brazing methods, only one vapor deposition process is required;
There are advantages such as the process can be simplified.
第1図は従来の半導体装置の製造方法を述べる
説明図、第2図はこの発明の一実施例を説明する
ための図、第3図はダイオードの製造例を示す説
明図である。
11……Si基板、12……電極金属、13a,
13b……Al−Ge……蒸着膜。
FIG. 1 is an explanatory diagram illustrating a conventional method of manufacturing a semiconductor device, FIG. 2 is an explanatory diagram illustrating an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing an example of manufacturing a diode. 11...Si substrate, 12...electrode metal, 13a,
13b...Al-Ge...deposited film.
Claims (1)
をロー付する方法において、前記Si基板及び電極
金属にAlとGeを同時に蒸着してAl−Ge蒸着膜を
形成し、その蒸着膜の組成がGe5〜30atm%とな
るようにするとともに前記Si基板と電極金属のロ
ー付温度が400℃〜600℃となるように設定し、し
かもロー付雰囲気が不活性ガス、水素ガスあるい
は真空中であるようにしたことを特徴とする半導
体装置の製造方法。1. In a method of brazing a Si substrate having an n-type diffusion layer on the surface and an electrode metal, Al and Ge are simultaneously deposited on the Si substrate and the electrode metal to form an Al-Ge deposited film, and the composition of the deposited film is determined. The brazing temperature between the Si substrate and the electrode metal is set to be 400°C to 600°C, and the brazing atmosphere is inert gas, hydrogen gas, or vacuum. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147549A JPS5848928A (en) | 1981-09-18 | 1981-09-18 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147549A JPS5848928A (en) | 1981-09-18 | 1981-09-18 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5848928A JPS5848928A (en) | 1983-03-23 |
| JPS6317332B2 true JPS6317332B2 (en) | 1988-04-13 |
Family
ID=15432830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56147549A Granted JPS5848928A (en) | 1981-09-18 | 1981-09-18 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848928A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5050440B2 (en) * | 2006-08-01 | 2012-10-17 | 日産自動車株式会社 | Semiconductor device and manufacturing method thereof |
-
1981
- 1981-09-18 JP JP56147549A patent/JPS5848928A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5848928A (en) | 1983-03-23 |
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