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JPS6035828B2 - Manufacturing method for resin-encapsulated integrated circuit device - Google Patents
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JPS6035828B2 - Manufacturing method for resin-encapsulated integrated circuit device - Google Patents

Manufacturing method for resin-encapsulated integrated circuit device

Info

Publication number
JPS6035828B2
JPS6035828B2 JP58016068A JP1606883A JPS6035828B2 JP S6035828 B2 JPS6035828 B2 JP S6035828B2 JP 58016068 A JP58016068 A JP 58016068A JP 1606883 A JP1606883 A JP 1606883A JP S6035828 B2 JPS6035828 B2 JP S6035828B2
Authority
JP
Japan
Prior art keywords
tab
integrated circuit
resin
frame
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58016068A
Other languages
Japanese (ja)
Other versions
JPS58151050A (en
Inventor
秀夫 稲吉
喜昭 若島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58016068A priority Critical patent/JPS6035828B2/en
Publication of JPS58151050A publication Critical patent/JPS58151050A/en
Publication of JPS6035828B2 publication Critical patent/JPS6035828B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は集積回路のレジン封止技術に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin encapsulation technique for integrated circuits.

レジンモールド型IC(半導体集積回路装置)は、複数
個のICに必要とするりードを一体に形成したりードフ
レームを用意し、そのリードフレームの各タブ部に半導
体べレットを接続し、リードとべレツトの電極をコネク
タ線を介して接続し、次いでレジンモールドし、その後
、リードフレームの不要部を切断除去する方法により製
造される。
Resin-molded ICs (semiconductor integrated circuit devices) are manufactured by preparing a lead frame in which the leads required for multiple ICs are integrally formed, and connecting semiconductor pellets to each tab of the lead frame. The lead frame is manufactured by connecting the electrodes of the top via a connector wire, then resin molding, and then cutting and removing unnecessary parts of the lead frame.

従来において用いられたりードフレームの一例は第2図
に示される。
An example of a conventionally used cable frame is shown in FIG.

このようなりードフレームを用いてICを製造した場合
、次のような問題があった。
When ICs were manufactured using such a board frame, the following problems occurred.

レジンモールド直後の高い温度の状態から常温に冷却さ
れる間にリードフレームとしジンの熱膨張係数の不一致
(レジンの方が熱膨張係数が大きい)に基づきリードフ
レームの各モールド部でレジンの収縮力によってリード
が収縮する現象が生じ、それに起因してリードフレーム
に歪み、反りが発生し、いよいよレジンがリードフレー
ムから剥離するという問題があった。
While the resin mold is being cooled from a high temperature state to room temperature, the shrinkage force of the resin is applied to each mold part of the lead frame due to the mismatch in the thermal expansion coefficients of the resin (resin has a larger thermal expansion coefficient). This causes a phenomenon in which the leads shrink, which causes the lead frame to become distorted and warped, leading to the problem that the resin eventually peels off from the lead frame.

本発明はしジンモールドに際してのパッケージの反り、
歪みを少なくすることを目的とするものである。
Warpage of the package when molding according to the present invention,
The purpose is to reduce distortion.

このような目的を達成するために、本発明の一実施例は
、枠体(第1の枠体)間にタブがつられたDILタイプ
のリードフレームの外枠のタブリード接続部にスリット
を設けることにより、レジン封止時の応力を吸収しよう
とするものである。
In order to achieve such an object, one embodiment of the present invention is to provide a slit in the tab lead connection portion of the outer frame of a DIL type lead frame in which a tab is suspended between the frame bodies (first frame body). This is intended to absorb stress during resin sealing.

以下本発明を図示した実施例により説明する。第1図は
本発明の一実施例を示す。1は半導体べレット接続用タ
ブの周囲にビーム状に配列されたりード、2は半導体べ
レット接続用タブ、3はタブ2を保持するためのタブリ
ード、これらリード1、タブ2及びタプリード3を含め
てリード部と称する。
The present invention will be explained below with reference to illustrated embodiments. FIG. 1 shows an embodiment of the invention. Reference numeral 1 denotes a lead arranged in a beam shape around a tab for connecting a semiconductor pellet, 2 a tab for connecting a semiconductor pellet, 3 a tab lead for holding tab 2, and these leads 1, tab 2, and tape lead 3. This is collectively referred to as the lead section.

4はしジンモールドの際モールド部からしジンが流出す
るのを防止するためのタィバー、5は長手方向の両側面
部、6はその側面部に形成されたスリット、7は相隣接
するリード部相互間を仕切る枠体である。
4 is a tie bar for preventing the gin from flowing out from the mold part when molding, 5 is both side surfaces in the longitudinal direction, 6 is a slit formed in the side surface, 7 is a tie bar between adjacent lead parts. It is a frame that divides the space.

この枠体7はリードフレームの剛性を保つ等のために必
要なもので、これがないとりードの先端部が弱くなり、
製造工程中に折れたりするので設けられている。
This frame body 7 is necessary to maintain the rigidity of the lead frame, and without it, the tip of the lead becomes weak.
This is provided because it can break during the manufacturing process.

そして、この枠体7には幅0.1〜0.6肋のスリット
が設けられている。スリットを設けた理由は前述の如く
、リードフレームの各モールド部においてレジンの収縮
力によってリードが収縮する現象が生じ、それに起因し
てリードフレームに歪が生じるので、スリットによって
リードフレーム自体の剛性を弱め、その歪を吸収できる
ようにするためである。
This frame body 7 is provided with a slit having a width of 0.1 to 0.6 ribs. As mentioned above, the reason for providing the slits is that the leads contract due to the contraction force of the resin in each mold part of the lead frame, which causes distortion in the lead frame, so the slits reduce the rigidity of the lead frame itself. This is to weaken the distortion so that it can absorb the distortion.

すなわち、リードフレームの両側面5に設けたスリット
6は、リードフレームの長手方向に生ずる歪を吸収する
That is, the slits 6 provided on both side surfaces 5 of the lead frame absorb strain occurring in the longitudinal direction of the lead frame.

これによって、レジンの収縮力によってリードフレーム
が長手方向に収縮してリードフレーム全体が長手方向に
反ることを防止できる。これはICの信頼性や製造上の
作業性の向上に寄与する。また、枠体部7に設けたスリ
ット8は、リードフレームの幅員方向に生ずる歪を吸収
する。
This prevents the lead frame from shrinking in the longitudinal direction due to the shrinkage force of the resin and warping the entire lead frame in the longitudinal direction. This contributes to improving IC reliability and manufacturing workability. Furthermore, the slit 8 provided in the frame body portion 7 absorbs distortion occurring in the width direction of the lead frame.

これによって、パッケージの反りを防止できる。以上説
明したように、本発明によれば、レジンモールドに際し
てのパッケージの反り、歪みを少なくすることができる
ものである。
This prevents the package from warping. As described above, according to the present invention, it is possible to reduce warpage and distortion of the package during resin molding.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例に用いるリードフレームの平面
図である。 第2図は従来例を示すリードフレームの平面図である。
1……リード、2……タブ、3……タブリード、4・・
・・・・タィバー、5・・・・・・側面部、6…・・・
スリット、7・・・・・・枠体部、8・・・・・・スリ
ット。 第1図第2図
FIG. 1 is a plan view of a lead frame used in an embodiment of the present invention. FIG. 2 is a plan view of a lead frame showing a conventional example.
1...Lead, 2...Tab, 3...Tab lead, 4...
...Tie bar, 5...Side part, 6...
Slit, 7...Frame body part, 8...Slit. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1 互いに平行な一対の第1の枠体と、前記第1の枠体
間のほぼ中央に設けられた集積回路ペレツトを載置する
ためのタブと、前記タブを前記第1の枠体に直接又は間
接に支持するためのタブリードと、前記タブにその自由
端が近接されてなる複数のリードと、前記複数のリード
を一体的に前記第1の枠体に支持する連結片と、前記第
1の枠体の前記タブに対応する位置に長手方向に配設さ
れたスリツトよりなる単位フレームを複数個設けたリー
ドフレームを準備し、前記タブ上に集積回路ペレツトを
固着し、その後、前記各リードと集積回路ペレツトの各
端子を電気的に接続し、前記集積回路ペレツト、タブお
よび複数のリードとタブリードの1部をレジンによりモ
ールドすることを特徴とするレジン封止集積回路装置の
製造方法。
1 A pair of first frames parallel to each other, a tab for placing an integrated circuit pellet provided approximately in the center between the first frames, and a tab that is placed directly on the first frame. or a tab lead for indirect support, a plurality of leads whose free ends are close to the tab, a connecting piece that integrally supports the plurality of leads on the first frame, and the first A lead frame having a plurality of unit frames made of slits arranged in the longitudinal direction at positions corresponding to the tabs of the frame body is prepared, an integrated circuit pellet is fixed on the tabs, and then each of the leads is fixed. 1. A method of manufacturing a resin-sealed integrated circuit device, which comprises electrically connecting terminals of an integrated circuit pellet and molding the integrated circuit pellet, a tab, a plurality of leads, and a portion of the tab lead with resin.
JP58016068A 1983-02-04 1983-02-04 Manufacturing method for resin-encapsulated integrated circuit device Expired JPS6035828B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58016068A JPS6035828B2 (en) 1983-02-04 1983-02-04 Manufacturing method for resin-encapsulated integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58016068A JPS6035828B2 (en) 1983-02-04 1983-02-04 Manufacturing method for resin-encapsulated integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1033476A Division JPS5294074A (en) 1976-02-04 1976-02-04 Leading-in frame

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP61188411A Division JPS6249648A (en) 1986-08-13 1986-08-13 Manufacture of resin molded semiconductor device with lead frame
JP61188410A Division JPS6249647A (en) 1986-08-13 1986-08-13 Manufacture of resin-molded semiconductor device

Publications (2)

Publication Number Publication Date
JPS58151050A JPS58151050A (en) 1983-09-08
JPS6035828B2 true JPS6035828B2 (en) 1985-08-16

Family

ID=11906248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58016068A Expired JPS6035828B2 (en) 1983-02-04 1983-02-04 Manufacturing method for resin-encapsulated integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6035828B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264745A (en) * 1985-05-20 1986-11-22 Shinko Electric Ind Co Ltd Lead frame
US5168337A (en) * 1988-02-19 1992-12-01 Nippondenso Co., Ltd. Polycrystalline diode and a method for making the same

Also Published As

Publication number Publication date
JPS58151050A (en) 1983-09-08

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