JPS6036035B2 - Time display element driving method for multi-digit fluorescent display tube digital clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a time display element of a multi-digit optical display tube digital watch, in which a pulse signal of a predetermined duty cycle and a DC signal having the same voltage as the pulse signal are displayed on the optical display. A time display capable of causing a time display element to emit light without causing unevenness in the brightness of each time display element and the brightness of each segment when dimming is required such as at night by switching the voltage applied to each plate of a tube. The object of the present invention is to provide a device driving method.

A digital clock using a crab light display tube (hereinafter referred to as FLT) uses thermionic electrons emitted from a filament to a crab light body (a multi-digit time display element arranged in a straight line) facing the filament. It is designed to display the time by emitting light when you hit it.

Here, when using this type of digital clock at night,
Since the same luminous intensity as during the daytime is too bright, the voltage applied to the plates and grids is lowered than during the daytime. However, when used at night with the voltage lowered in this way, there is a potential difference between the potentials at both ends of the filament and the potential at the center of the filament, and a temperature difference due to heat diffusion between both ends of the filament and the center, as shown in Figure 1. As shown in Figure 2, the emission intensity of the time display element in the center becomes significantly higher than the emission intensity of the time display elements at both ends, or the emission intensity of segments within the same display element becomes uneven. There were some drawbacks, such as the time being difficult to read. In addition,
Figure 1 shows the ratio of the brightness of the element in the 1st digit to the brightness of the display element in the brightest central digit among the 4-digit display elements at a filament voltage of 1.7 V (i.e., the brightness ratio). Figure 2 shows the relationship between , plate voltage, and grid (control) voltage.
) (from the "1 minute" digit to the "1's exclusive digit") shows the relationship between the luminance of the device, the plate voltage, and the grid (control) voltage.

The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described with reference to FIG. 3 and subsequent figures. In the embodiment shown in FIG. 3, when the surroundings are bright, such as during the day, the dimming switch S is opened. The pulse from oscillator 1 is divided into 8 by frequency divider 2.
Pulse a of KH2 (Fig. 4A) and pulse b of 1 shoe HZ
The pulse c shown in FIG. 4C is taken out from the NAND circuit 3 and supplied to the AND circuit 4. On the other hand, the pulses taken out from the frequency divider 2 are supplied to a driver circuit 7 via a counter 5 and a decoder 6, and a drive signal is taken out by a well-known operation. When the switch S is opened, an L-level signal is taken out from the inverter 8 and supplied to the AND circuit 4, which is then supplied to the AND circuit 4. An L-level signal is taken out from the AND circuit 4 and is then applied to the depletion type MOSFE.
Supplied to T9. FET9 is turned on by the L level signal from AND circuit 4, and as a result, FLTI
A power supply voltage VDD is applied to the plate 11 of O (duty cycle 1'1, that is, a DC signal), and the display element 12a
(1st digit) to 12d (4th digit) emit light at a predetermined brightness,
The brightness ratio is 85% as shown in FIG. In FIG. 3, 13 is a filament and 14 is a grid. In addition,
Figure 5 shows the relationship between the luminance ratio (brightness ratio) of the first digit display element to the brightest display element among the four digit display elements and the duny cycle of the plate voltage at a filament voltage of 1.7V. show. Further, the luminance of the display element of each digit in this case is as shown in FIG. When the surroundings are dark, such as at night, when switch S is closed, inverter 8
A high level signal is taken out, and a pulse c shown in FIG. The pulse c is supplied to the FET 9, and a pulse signal d having a voltage VDo, a frequency of 8KH2, and a duty cycle of 1/4 as shown in FIG. ~12d emits light at substantially lower luminance than daytime. Note that the output oscillation frequency of the oscillator 1 and the power supply voltage Voo are always constant. That is, the plate voltage is the same as in the daytime, but since the duty cycle is lower than in the daytime, the time for which electricity is applied to the plate 11 is correspondingly shorter, and the afterimage effect causes a substantial impact on the human eye. It seems that the brightness of the display elements 12a to 12d has become lower.

In this way, according to the present invention, the same plate voltage is used at night as during the day, so the potential difference between the voltage at both ends of the filament and the voltage at the center of the filament and the thermal diffusion caused by lowering the voltage as in the conventional case are reduced. There is no difference in luminance due to temperature differences, etc., and as shown in Figure 5, there is no difference between the luminance ratio when the duty cycle is 1/1 (DC signal) and the luminance ratio when the duty cycle is 1/4. does not occur.

In addition, as shown in Figure 6, the brightness of the display elements of each digit decreases uniformly as the duty cycle decreases, so there is no uneven brightness of each digit as in the conventional case, and the display elements of each digit decrease uniformly as the duty cycle decreases. There is no unevenness in the brightness of segments within the same area. Although the duty cycle in this embodiment is 1/4, it is not limited to this, and various duty cycles can be freely selected by appropriately selecting the frequency division ratio of the frequency divider 2. obtain.

In this case, the lower limit of the duty cycle is hardly required to be ⅛ or less, taking into account the afterimage effect of the eye. Also, the upper and lower limits of the plate voltage frequency that can actually be used are:
Approximately 32Hz to 2 days after leaving Japan.

That is, if the frequency is too low, the display will blink, and if the frequency is too high, the pulses will be substantially continuous, so that even if the duty cycle is lowered, it will not appear that the brightness has been lowered. As described above, the method for driving a time display element of a multi-digit optical display tube digital watch according to the present invention divides the frequency of a pulse from a time display pulse oscillator to obtain a pulse signal of a predetermined voltage and a predetermined duty cycle. By switching and applying the signal and the DC signal of the predetermined voltage value to the plates of the light display tube, the luminance of the time display element is made different, so when using it at night, the same voltage applied during the day can be applied. - If a pulse signal with a low cycle is applied, the brightness of each display element appears to be substantially lowered without causing unevenness in the brightness of each digit of the display element and the brightness of each segment of the display element, and therefore, Compared to conventional clocks, it has the advantage of being easier to read the time, and because the duty cycle of the plate voltage is changed, which is smaller than the grid (control) voltage, each element of the LSI can be made smaller.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing the luminance ratio of the time display element versus the plate voltage of the crab light display tube, grid (control) voltage characteristics, and each display element, respectively, to explain the operation of a conventional crab light display tube digital watch. The luminance vs. plate voltage and grid (control) voltage characteristic diagrams of FIGS. 3 and 4 A to 4D each illustrate a driving circuit diagram used in one embodiment of the time display element driving method according to the present invention and its operation. FIGS. 5 and 6 are voltage waveform diagrams showing the luminance ratio of the display element versus the duty cycle of the plate voltage of the rear light display tube, respectively, for explaining one embodiment of the time display element driving method according to the present invention. FIG. 4 is a characteristic diagram and a duty cycle characteristic diagram of brightness versus plate voltage of each display element. 1... Oscillator, 2... Frequency divider, 3... NAND circuit, 4... AND circuit, 7... Driver circuit, 8... Inverter, 9... FET, 10... Halo display Tube, 11...
Plate, 12a-12d... Time display element, S...
・Switch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. In a method for driving a time display element of a multi-digit fluorescent display tube digital watch in which a voltage is applied to the plate of a fluorescent display tube to cause time display elements arranged in parallel in multiple digits to emit light, a pulse from a time display pulse oscillator is used. The time is displayed by frequency-dividing the frequency to obtain a pulse signal of a predetermined voltage and a predetermined duty cycle, and applying this pulse signal and a DC signal of the predetermined voltage value to the plate of the fluorescent display tube by switching between them. A method for driving a time display element of a multi-digit fluorescent display tube digital watch, characterized in that the luminance of the elements is varied.