JPS623912B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a dynamic display type electronic timepiece using a FLourescent (hereinafter referred to as FL) display tube, and in particular to preventing flickering of the time display.

Conventionally, FL display tubes have been used in the display section of watches. An FL display tube heats a heater inside the display tube to emit electrons, and the emitted electrons are applied to a fluorescent material coated inside the tube to emit light. Therefore, as the heater current increases, the amount of electron emission also increases, and the brightness of the FL display tube increases accordingly. Traditionally, watches using FL display tubes were powered by AC power (50Hz or 60Hz) due to current consumption.
Hz) is often used, and for this reason, the brightness of FL display tubes changes according to the AC power supply voltage, but the change is too fast for the human eye to see, and it is difficult to maintain a certain level of brightness. appear. However, when the time display method of a watch is a dynamic drive method, the dynamic drive frequency is set to 1 commercial frequency (50Hz or
60Hz) If the dynamic drive frequency L is set to less than 20Hz, the human eye will perceive flickering.

FIG. 1 is a waveform diagram showing changes in brightness of an FL display tube when using AC power frequency and dynamic drive. In Figure 1, curve a shows the output waveform of the AC power supply, and A is its period (1/50 in Figure 1).
seconds). Here, if the period of the digit drive voltage is B, then the FL display tube will be at points b1 and b on the AC power supply waveform A.
Lights up at 2, b3, b4, b5, and b6. Connecting these points b1, b2, b3, b4, b5, and b6 results in a waveform of curve C, and the brightness of the FL display tube changes according to the waveform of curve C. The frequency of this curve C has a value of 1 commercial frequency 1 dynamic drive frequency 1, and when this frequency becomes 20 Hz or less, it becomes visible to the eyes as flickering.

Conventionally, in order to eliminate this flickering, a high frequency of several hundred Hz was used for the digit drive voltage, but this created a new problem in that it caused noise from nearby radios, etc.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to prevent flickering in the time display of a dynamic display type electronic timepiece using an FL display tube.

In order to achieve the above object, the present invention detects the peak time of the output waveform of an AC power supply and performs a dynamic display at this peak time to synchronize the brightness change of the FL display tube with the dynamic display. Features.

The present invention will be described in detail below based on preferred embodiments. FIG. 2 is a block diagram showing an embodiment of the present invention. The clock circuit 29 includes a reference signal generator 22, a frequency divider 24, a sexagesimal counter 26, and a 24-decimal counter 2.
8 to form a time signal corresponding to the time display digit. The reference signal generator 22 is a circuit that generates a time reference signal, and the frequency divider 24 is a circuit that divides the frequency of the time reference signal into a signal with a period of one minute. The sexagesimal counter 26 is a counter that counts minutes based on the signal from the frequency divider 24, and the 24-decimal counter 28 is a counter that counts hours.

In the display section 38, AC voltage is applied to the heater.
It consists of an FL display tube and displays the time based on the time signal from the clock circuit 29.

The scanning signal generation circuit 57 is a flip-flop 5.
0, 54, 56 and a demultiplexer 32, and sequentially outputs scanning signals 66 to 72 for selecting each time display digit of the display section 38 at a predetermined period. That is, flip-flops 52, 54, and 56 constitute a counter, and the count value "1" to
Scanning signals 66 to 72 are output corresponding to "4".

The display drive circuit 37 is connected to the multiplexer 3.
0, a decoder 34, a segment drive circuit 36, and a digit drive circuit 60, and dynamically drives the display section 38. The multiplexer 30 uses the aforementioned scanning signals 66 to 72 to output the 24-base counter 2.
The signal of the 10th digit of the hour from 8 and the signal of the 1st digit, and the signal of the 10th digit of the sexagesimal counter 26 and 1
The signals of the digits are sequentially supplied to the segment drive circuit 36 via the decoder 34. At the same time, the scanning signals 66 to 72 are also supplied to the digit drive circuit 60. Therefore, the display section 38 displays the scanning signal 66.
A segment drive voltage and a digit drive voltage are applied in synchronization with 72, thereby displaying the time.

The detection circuit 45 includes a phase conversion circuit 40 and a comparison circuit 44, and outputs a detection signal 62 at each peak of the AC voltage applied to the heater. The phase conversion circuit 40 changes the phase of the output signal from the AC power supply 42 to 90
The comparison circuit 44 is composed of a Schmitt trigger circuit, etc., and when the potential of the signal from the phase conversion circuit 40 exceeds zero potential, a signal of a positive high potential (hereinafter referred to as H) is sent to the oscillation circuit 46. Output.

The display control circuit 49 is composed of an oscillation circuit 46, an AND gate 48, and a NAND gate 52, and generates scanning signals 66 to 7 in response to the output of the detection signal 64 described above.
This circuit sequentially outputs 2 and stops outputting the scanning signal when it detects that all the time display digits on the display section 38 have been selected. The oscillation frequency signal of the oscillation circuit 46 is passed through the AND gate 48 to the flip-flop 5.
A counter consisting of 0, 54, 56 is fed.
Further, the output line 74 of a NAND gate 52 is supplied to the other input terminal of the AND gate 48, and the Q outputs of the flip-flops 50 and 56 and the output of the flip-flop 54 are supplied to the NAND gate 52.

The operation of this circuit will be explained below. The 50 Hz or 60 Hz signal output from the AC power supply 42 is phase shifted by 90 degrees by the phase conversion circuit 40 and applied to the comparator circuit 44 via the output line 62. Here, when the 90 degree phase shifted AC signal applied to the comparator circuit 44 becomes higher than zero potential, the comparator circuit 4
A signal that goes to H level is generated on the output line 64 of No. 4 from the low potential side (hereinafter referred to as L). At this time, the value of the signal from the AC power supply 42 has just reached its peak. At this time, the oscillation circuit 46 operates and the resets of the flip-flops 50, 54, and 56 are released. Then, the counter consisting of flip-flops 50, 54, and 60 starts counting the oscillation frequency from the oscillation circuit 46, and the counter consisting of flip-flops 50, 54, and
The Q output signals of 6 and 54 are applied to a demultiplexer 32. and flip flop 50,5
When the output signals of 6 and 54 are H, L, and L, the signal of the output line 66 of the demultiplexer 32 changes from L to H.
This causes the multiplexer 30 to
Select the signal for the 10th digit, and also use the digit drive circuit 60.
drives the signal for the 10th digit of the hour. As a result, only the 10th digit of the time is displayed on the display section 38. Similarly, after this, the signals of the flip-flops 50, 54, 56 become L, H, L, then H, H, L, then L, L, H, and accordingly, the output lines 68, 70 of the demultiplexer 32,
The signal 72 sequentially changes from L to H. The multiplexer 30 sequentially outputs signals for the first digit of the hour, the tenth digit of the minute, and the first digit of the minute, and the digit drive circuit 60 also sequentially outputs signals for the first digit of the hour and the tenth digit of the minute. digit,
The first minute digits are driven sequentially. This result display section 3
At 8, the 1st digit of the hour, the 10th digit of the minute, and the 1st digit of the minute light up in sequence. Then, when the signals of the flip-flops 50, 54, and 56 change to H, L, and H, the signal of the output line 74 of the NAND gate 52 changes from H to L, and the AND gate 48 is closed. Then, the comparator circuit 64 in which the signal on the output line 62 becomes equal to or less than zero potential.
The signal goes from H to L, stopping oscillation of oscillator 46 and resetting flip-flops 50, 54, and 56. Thereafter, the above-described operation is repeated every time the signal of the AC power supply 42 reaches a peak.

This series of operations is performed at 1/50 or 1/60 seconds, which is the cycle of the AC power supply, so to Shima's eyes, the hours and minutes appear to be displayed at the same time.

FIG. 3 is a time chart in FIG. 2. As can be seen from FIG. 3, when the voltage value from the AC power supply 42 reaches its peak, the output lines 66, 68, 70, and 72 of the demultiplexer 32 sequentially change from L to H, and the 10th digit of the hour and the first The digit, the 10th digit of the minute, and the 1st digit of the minute are displayed in sequence. Therefore, since the time is always dynamically displayed on the display section 38 using the FL display tube when the brightness reaches its peak, it is possible to prevent flickering, which has been a problem in the past.

Figure 4 shows the Central Processing Unit (CPU
FIG. 2 is a block diagram showing another embodiment of the present invention using the following.

The reference signal generator 80, frequency divider 81, segment drive circuit 82, digit drive circuit 84, display unit 86 using an FL display tube, AC power supply 88, phase conversion circuit 90, and comparison circuit 92 are as shown in FIG. Same as in case. The CPU 94 counts the time using the reference signal from the reference signal generator 80, and outputs the counted time signal to the segment drive circuit 82 and the digit drive circuit 84 based on the interrupt signal from the comparison circuit 92, and displays the time on the display unit 38. This is a circuit that displays.
The control program 96 is a circuit that controls the operation of the CPU 94, and the input key 98 is an external operation member used to initialize or modify the time display.

The operation will be explained below using the flowcharts shown in FIGS. 5a and 5b. First, the CPU 94 determines whether a reference signal for time measurement has been received from the frequency divider 81 (corresponding to step 100). If the reference signal has not arrived here, the process returns to step 100. When the reference signal is received, the CPU 94 measures the time based on the time reference signal (corresponding to step 102). Here, when the phase conversion circuit 90 and the comparison circuit 92 detect the peak time of the output voltage value from the AC power supply 88, the signal of the comparison circuit 92 rises from L to H, but the CPU 94 treats this signal as an interrupt signal. , enters the interrupt processing program of FIG. 5b. First of all, CPU
94 outputs a time signal for the 10th digit of the hour to the segment drive circuit 82, and outputs a signal for driving the 10th digit segment of the hour to the digit drive circuit 84 (corresponding to step 104). Next, the CPU 94 sends the time signal of the first digit of the hour to the segment drive circuit 82.
A signal is outputted to the digit drive circuit 84 to drive the first digit of the hour (corresponding to step 106). Then, the time signal of the 10th digit of the minute and the 1st digit of the minute is sequentially output to the segment drive circuit 82, and the 10th digit of the minute and the 1st digit of the minute are sequentially output to the digit drive circuit 84. A driving signal is output (corresponding to steps 108 and 110). As a result, the display section 86 composed of an FL display tube displays the hour 10.
The numbers are displayed sequentially as the first place digit, the first place digit, the tenth place digit of the minute, and the first place digit. Since this series of operations is performed at the frequency (50Hz or 60Hz) of the AC power source 88, they appear to be displayed simultaneously to the human eye. Thereafter, the program returns to the main program shown in FIG. 5a again and determines whether the reference signal has arrived (corresponding to step 100). Thereafter, the above operation is repeated.

As described above, according to this embodiment, since the time is always displayed on the display unit 86 using the FL display tube when the brightness reaches its peak, it is possible to prevent flickering, which has been a problem in the prior art.

In a watch that uses an FL display tube for the time display section 86 and uses the CPU 94 for the time measurement mechanism as in this embodiment, the dynamic drive frequency of the display cannot be as high as several hundred Hz. Therefore, the present invention provides a very effective flicker prevention means for such watches.

As described above, according to the present invention, the time is always displayed when the brightness of the FL display tube reaches its peak, making it possible to prevent flickering, which has been a problem with conventional dynamic display watches. Also
The electronic energy of the FL display tube heater can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is an AC voltage waveform diagram. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a time chart in FIG. 2. FIG. 4 is a block diagram showing another embodiment of the present invention. Fifth
The figure is a flowchart of FIG. 4. 22, 80...Reference signal generator, 24, 81...
...Frequency divider, 38, 86... Display section, 42, 88...
...AC power supply, 40,90...Phase conversion circuit, 4
4, 92... Comparison circuit, 46... Oscillation circuit, 58
... Quintal counter, 32 ... Demultiplexer,
94...CPU, 96...Control program.

Claims (1)

[Scope of Claims] 1. A clock circuit that clocks a reference signal to form a time signal corresponding to a time display digit, and an FL display tube to which an AC voltage is applied to a heater and displays the time based on the time signal. a scanning signal generation circuit that outputs a scanning signal for sequentially selecting each of the time display digits at a predetermined period; a digit drive voltage that sequentially outputs a digit drive voltage to the display section in synchronization with the scanning signal; a display drive circuit that dynamically drives a display unit by applying a segment drive voltage based on 2. A dynamic drive display timepiece, comprising: a display control circuit that starts outputting the scanning signal when the time display is selected, and stops outputting the scanning signal when detecting that all time display digits have been selected.