JPS6038797B2 - sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier, and more particularly to a sense amplifier that can read the output of a semiconductor memory device at high speed.

As the capacity of read-only memory devices (hereinafter abbreviated as ROM) and random access memory devices (hereinafter abbreviated as RAM) increases, the output parasitic capacitance of memory cells increases, and the charging and discharging times become longer. A sense amplifier is required to ensure operation.

As shown in Figure 1, a conventional sense amplifier is constructed by vertically connecting an insulated gate field effect transistor (hereinafter simply referred to as a transistor) to which a constant potential Vcc is applied to a control electrode and a transistor which applies an input to the control electrode. Something like a level shifter is used.

However, for a programmable ROM, that is, a PROM, which has a small output level difference, the sensitivity is low and high-speed operation cannot be expected. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-speed sense amplifier. Hereinafter, the present invention will be described according to examples and with reference to the drawings. In FIG. 2, the gate and drain of the tebretion type transistor T, are commonly connected and led to the power supply Vcc, and the source of T, is connected to the drain of the enhancement type transistor T2. The gate and source of T2 are respectively connected to T. connected to the gate and ground point. The input signal to be compared, that is, the output signal of the memory cell, is the source of T, and the source of T2.
is led to the gate of the enhancement type transistor T3 through the drain connection point A of the transistor T3. A depletion type load transistor T4 whose gate and source are connected is connected to the drain of T3. In addition, in a circuit of the same type as the circuit consisting of T and T2, point B, where the source and drain are connected, is used as a reference output, and the output of point B is connected to the gate of transistor T5, and its drain is connected to T.
A load MOST 6 similar to the load MOS connected to MOS 3 is connected. The drain of a transistor T7 is commonly connected to the sources of T3 and T5, and the source of this transistor is grounded. The gate and drain of T9 are connected to the point C where the gate and source of the depression type transistor T8 are connected, and the source of T9 is grounded. Note that point C is connected to the gate of T7. If point A is pulled to a low level, the current m.
is limited, and point D is at a high level. Current I flowing through L
D3 is the current that flows through L and T5, and since T7 is a constant current type transistor, the current that flows through T5 relatively is ID2.
becomes large and the E point becomes a low level. Furthermore, when point A becomes high level, the current m flowing through T3 becomes large, and point D becomes low level. The current ID2 flowing through T5 is relatively limited, and the E point is at a high level. In FIG. 3, curve F is the load characteristic curve of T4 and L.

Curves G, Day and 1 show the operating characteristics of T3 and T5. Curve 1 is T3 and T5 with no input applied to point A.
, and ID and ID2 have the same current value. When point A is set to a low level, the operating characteristic of T3 becomes like a curved line, and the level of point D becomes the intersection point J(V) of F and day. In this case, the operating characteristic of L is as shown by curve G, and the level at point E is the intersection point K(V) of F and G. Note that when point A is set to a high level, the above-mentioned reverse phase occurs. As can be seen from the above, the sensitivity of the present sense amplifier can be controlled by changing the current values flowing through T3 and T5 when no input is applied to point A.

Since the current value flowing through T3 and above is controlled by T7, the current value can be easily set by changing the voltage applied to the gate of T7. By the way, the second
Since the potential at point F in the diagram does not reach a completely low level, the potentials at points D and E also do not reach a completely low level, so the level is shifted by the differential amplifier shown surrounded by a dotted line.

To explain the configuration of this reed amplifier, there are transistors T whose sources are commonly connected and grounded. and T,. The drains of T,2 are commonly connected to the sources of T,2, and the drains of T,2 are connected to Vq. Similarly, transistors T,3, T,4, and T,5 constitute the same type of circuit, and the gates of T,2 and T,4 are connected to the output OUT at point D.
is supplied to the gates of T,5 and T,o, and the output O of point E is supplied to the gates of T,5 and T,o.
UT is supplied. T,. The gates are T, 3 and T
, 4 is connected to a common connection point 8 between the drains of T and 5, from which an output OUT' is obtained, and similarly T
, 3 are T,o and T, . It is connected to a common connection point D' between the drain of T and the source of T,2, from which an output OUT' is obtained. If the potential at point A in Figure 2 changes as shown in waveform A in Figure 4 a, the potential at point D in Figure 2 changes as shown in Figure 4 b.
The waveform changes as shown in ○.

In that case, the potential of the output at point 0 becomes approximately equal to the value obtained by subtracting the function voltage VT of transistors T and 2 from the potential at point D, and changes as shown by waveform D' in FIG. 4b. Similarly, the potential at point E' becomes almost equal to the value obtained by subtracting VT from the potential at point E (waveform E' in Figure 4c), and a high enough level can be obtained to drive the next stage transistor. . As explained above, according to the present invention, since a differential amplifier is used, there is a significant effect in increasing the sensitivity and speed of the sense amplifier.

It goes without saying that the above description using an N-channel transistor may also use a P-channel transistor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional sense amplifier, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a curve diagram showing the operating characteristics of transistors T3 and T5, and FIGS. 2
FIG. 3 is an operation waveform diagram of the circuit surrounded by dotted lines in the figure. Vcc...power supply, T,,T2,t,L...tepletion type insulated gate effect transistor, L,T3,L,T
7,T9,T,,,T,2,T,3,T,4,T,5,
``Enhancing type insulated gate field effect transistor. 4th boxLeopard 1 figure Leopard 2 figure Chrysanthemum 3 figure

Claims (1)

[Claims] 1 Applying a comparison input and a reference input to the gates of first and second insulated gate field effect transistors whose sources are commonly connected, respectively, and extracting the level difference between these two inputs from each transistor accordingly. A sense amplifier characterized in that two outputs having mutually opposite phases are outputted through a level shift circuit connected in a differential format.