JPS6038798B2 - Non-volatile semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION '1] Technical field of the invention The present invention relates to a non-volatile semiconductor memory circuit, particularly an EEPROM.
(Electric Erasable Progra
The present invention relates to a mmableRead-OnlyMemory) circuit.

■Technical Background In recent years, electrically programmable and erasable nonvolatile semiconductor memory circuits have come into widespread use.

This is because there is no inconvenience such as using ultraviolet light. A sectional view of its structure is shown in FIG. SUB is a substrate, S and D are source and drain regions, 1 is an insulating film, and FG and CG are floating gates and control gates. The principle of writing and erasing is the so-called tunnel effect, which relies on a thin film 1' formed between the floating gate FG and drain D of the MOS transistor constituting the memory cell. A control gate CG coupled with a capacitor is further provided on the floating gate FG, and by changing the voltage level to be applied to the control gate CG, drain D, etc., write mode, read mode, and erase mode are set. In this case, the voltage applied to the control gate CG, that is, the erasing voltage,
As the write voltage and the read voltage, voltages generated from a voltage generating means to be described later are applied to the control gate of a designated MOS transistor cell through a control gate selection column line. In a nonvolatile semiconductor memory circuit, one important issue is how efficiently a control gate voltage can be applied to the MOS transistor cell. '3} Prior Art and Problems Figure 1 is a circuit diagram showing the entirety of a general nonvolatile semiconductor memory circuit.

The non-blind semiconductor memory circuit 10 has a bias circuit portion 11
and a plurality of column selection lines 12i.
, 12j (only two are shown), a plurality of row wires 13k, 1
31 (only two shown) and a plurality of bit lines B, . ,B2
,...88, Single,...Equipped with B prisoners. At the intersections of the row lines 13k, 131 and the bit lines B, . . . , a memory cell consisting of a bare MOS transistor 4 and a selection transistor 22 for selecting the MOS transistor 4 shown in FIG. 3 is provided. The selection transistor 22 is connected to the row lines 13k, 131
and bit line B. . . , the storage MOS transistor 4 is connected in series with the selection transistor 22, and its source is connected to the source potential determining circuit 21. Eight memory cells constitute one unit (l by), and the control gates of each unit are column gate transistors 5i, 15j, column line CGS for control gate selection, and row control gate selection transistors 6kl, 16k2, 1611, 161
A voltage generating means 201 is connected through the terminal 2.

CL○,. ...CL○, 8, CLC2. ...CLG
28 is a column selection transistor which connects bit lines B, . ...B
28 to the output bus 17 (an 8-bit bus is shown).

Then, output bus 17 has a bit-compatible sense amplifier circuit (
18 inches is an input section, and 1 inch is an output section) 18 (only 1 bit out of 8 bits is shown) is provided, and data Dout is output from an output buffer circuit 19. At the time of writing, the selection transistor 22 of a desired memory cell group is turned on, a write signal W is applied by the voltage generating section 20, the transistor Qw is turned on, and the ground potential GND is generated.

This potential is applied to the control gate CG of a designated cell group (every 8 bits) via the column gate transistor 5, the column line COS for control gate selection, and the row control gate selection transistor 6. At the time of erasing, the voltage generating section 20' is given the iron erasing signal E, turns on the transistor QE, and generates a voltage VPP of, for example, 20V.
is generated and similarly applied to the control gate CG of the designated cell group. At the time of data entry, the readout signal R is applied to the voltage generator unit 2, which turns on the transistor QR, generates a predetermined bias voltage, and applies it to the control gate CG to read out the 8 bits of the specified cell group. Read the contents of in parallel. By the way, the above-mentioned non-volatile semiconductor memory circuit has two problems.

'1} The voltage VPP at the time of erasing (for example, 20V
) is the control gate C of MOS transistor 4
It is not applied exactly as O, but is applied at a reduced level, for example to about 18V.

For this reason, erasure errors may occur. '2)
The speed of discussion is slow.

The reason for the above problems (1) and '2) is that the column gate transistor 15 and the row control gate selection transistor 16, which are mainly enhancement type MOS transistors, are used.

Since it is an enhancement type, the erase voltage (20V) that passes through this gate is lower than its threshold level voltage Vtn (approximately IV) than the potential of the gate to which the same voltage is applied.
It will be attenuated by that amount. This causes problem m mentioned above. Furthermore, since the transistors 5 and 16 between the voltage generating means 20 and the control gate are enhancement type MOS transistors, each of them is completely turned on after a signal for selecting them is applied to each gate. The delay time until the battery is fully charged and the charging time for the control gate capacity, etc., are unavoidable, giving rise to the above-mentioned problem (2). OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to propose a nonvolatile semiconductor memory circuit in which the erase voltage VPP is not attenuated and the read speed can be improved.

■Structure of the Invention In order to achieve the above object, the present invention comprises a column gate transistor and an o control gate selection transistor between the voltage generating means 20 and the control gate CG, both of which are depletion type MOS transistors. It is characterized by this.

'6} Examples of the invention The present invention will be explained using the drawings.

FIG. 2 is a circuit diagram showing only the portion of FIG. 1 to which the present invention is applied. In this figure, the same components as in FIG. 1 are designated with the same reference numbers (symbols).
As shown in this diagram, the enhancement type MOS shown in Figure 1
Column gate transistor 5i consisting of transistors
, 15j and the row control gate selection transistors 6kl, 16k2, 1611, 1612, etc. are depletion type MOS transistors 25i, 25j, respectively.
, 26kl, 26k2, 2611, 2612, etc. These depletion type MOS transistors usually have a threshold level voltage Vth of about -2V.
Since it has a normally-on shape, the above-mentioned problem m is solved. Also, unselected MOS transistor
4, even if it is not selected, its control gate voltage is already set at a level that is approximately 2V higher than the gate potential OV of transistors 45, 26, etc. by IVthl. Then, when the battery is actually selected, since charging has progressed considerably, it takes almost no time to reach the read state completely. This solves the above problem {2). (7) Effects of the Invention As explained above, according to the present invention, a nonvolatile semiconductor memory circuit that does not involve attenuation of the erase voltage and is capable of high-speed reading is realized.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the entirety of a general non-volatile semiconductor memory circuit, Figure 2 is a circuit diagram showing only the portion of Figure 1 to which the present invention is applied, and Figure 3 is a circuit diagram of a conventional memory cell. FIG. 2 is a cross-sectional view of a MOS transistor. DESCRIPTION OF SYMBOLS 10... Nonvolatile semiconductor memory circuit, 20... Voltage generating means, 12i, 12i... Column selection line, 13k
, 1 3 1... o line, 1 4... MOS transistor, 25i, 25i... column gate transistor,
26kl, 26k2, 2611, 2612...Row control gate selection transistor, FG...Floating gate, CG...Control gate. Figure 2 Figure 1 Figure 3

Claims (1)

[Claims] 1 A MO comprising a plurality of bit lines, a plurality of row lines, and an MO provided at the intersection of the bit lines and the row lines, each of which has a built-in floating gate and a control gate.
A MOS transistor comprising a nonvolatile memory cell group including S transistors, and voltage generation means for generating a predetermined voltage to be applied to the control gate, and provided between the control gate and the voltage generation means. 1. A nonvolatile semiconductor memory circuit comprising a depletion type MOS transistor.