JPS6040709B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a semiconductor memory device called a charge pumping memory (see Tokuka Sho 52-70862).

In this type of storage device, one memory cell has one SO
It is composed of an S-type MOS transistor, and the apparent threshold voltage y ratio changes due to the back gate effect depending on whether or not charge is accumulated in the floating channel region, and the voltage between the source and drain and When a voltage is applied between the source and gate, a difference occurs in the drain current lo, so
By reading the difference, it is possible to determine the information of a specific cell.

Writing is then performed by injecting fin charges from the channel region (inversion layer). By the way, a drawback of such memory counterfeiting is that the accumulated charge in the floating channel region disappears in a short time due to the large junction IJ current peculiar to SOS.

Since junction leakage current is small in a bulk type MOS transistor, if an SOS type MOS transistor is to be replaced with it, a new junction is required to separate the channel region from the substrate and keep it floating. The junction needs to have a large area, including the source and drain regions. Therefore, although the leakage current per unit area in the junction is smaller than that of the SOS type, since the area is large, the overall leakage current is large, and it is difficult to improve the charge retention time. Can not. The present invention provides a transistor (80 MO
This is intended to extend the information retention time by configuring the device using S transistors, and this will be explained in detail below.

FIG. 1 is an explanatory view of an embodiment of the present invention.

In the figure, 1 is an n-type semiconductor substrate, 2 is an epitaxially grown p-type semiconductor layer, 3 is a buried oxide layer, 4 is an epitaxially grown p-type single crystal semiconductor layer, and 4' is a polycrystalline semiconductor layer. 5 is an insulating isolation region, 6 is a gate oxide film, 7 is a silicon gate electrode, 8 is an n-type source region, 9 is a bald-type drain region, S is a source electrode, D is a drain electrode, G
is the gate electrode. In addition, the source Kame pole S is the bit line B
L, the drain electrode D is the pre-charge line (power supply) PL
In addition, the gate electrodes G are connected to word lines W, respectively. This device operates as follows.

Note that Voo indicates the power level. Source Gate Drain (Low.Relire) o Chi.

→ o writing (fall far away) VDD thing/Ashira level).

Heart D→. 〇 (Slow fall) Read O VoD VDo
In the above operation example, a so-called charge pump effect is utilized.

That is, during low level writing, the gate voltage is suddenly dropped from a voltage above the threshold value to 0 with Voo applied to the drain, so that the electrons existing in the channel are transferred to the epitaxial layers 2 and 4 (hereinafter referred to as A large amount remains in the channel forming region (referred to as a channel forming region), and changes its potential, resulting in a change in the threshold voltage Vth on the neck due to the back gate effect. On the other hand, when writing to a high level, the gate voltage changes slowly, so the charge as described above occurs.
No pump effect occurs, and no negative charges accumulate in the channel forming region. At this time, the voltage applied to the drain is V even if it is 0. It may be D. At the time of writing, if a predetermined voltage V is applied to the gate and drain and the current flowing between the source and drain is detected, if a back gate effect occurs due to low level writing, the state will be set to high level writing. Since a comparatively smaller current flows, for example, only 1/2, it is possible to detect 1 and 0.

After reading is completed, in order to avoid destruction of the memory, it is preferable to slow the rise of the gate voltage to prevent the charge pump effect from occurring.

In order to perform erasing, for example, a voltage sufficient to cause an avalanche may be applied between the source and drain to inject holes into the channel forming region by avalanche, thereby canceling out the accumulated electrons. In addition to the charge pump effect, formation avalanche injection or the like can also be used for injecting charge into the channel forming region and writing, and the write initiation operation is not limited to the above example.

In this embodiment, since the junction for separating the channel formation region from the substrate 1 is formed only on the lower side of the channel region, its area is smaller than that of a normal bulk MOS transistor when attempting to separate the pn junction of the same device. In addition, the leakage current per unit area in the junction is as small as in a normal bulk type MOS transistor.

Next, a case of manufacturing an embodiment of the present invention will be briefly described. See Figure 2 '1' For example, 0.5 [Q arc], (100), about 2 [0 skin] for the n-type silicon semiconductor substrate 1, and about 5000 [A] for the p-type silicon semiconductor layer 2. grow epitaxially.

(2) Selective thermal oxidation is performed using, for example, a nitrification mask to form an oxide layer 3 that reaches the substrate 1.

This becomes an oxidized layer. Refer to FIG. 3. [31 For example, a p-type silicon semiconductor layer is epitaxially grown to about 20 [Q/skin].

As a result, a single crystal semiconductor 4 is grown on the semiconductor layer 2, and a polycrystalline semiconductor layer 4' is grown on the oxide layer 3. [4
1. Selectively oxidize polycrystalline semiconductor layer 4' to form insulating isolation region 5. This makes each memory cell independent. [51] Thereafter, conventional techniques, ie, techniques for forming silicon gate n-channel MOS transistors, are applied to complete the device as seen in FIG.

That is, the formation of the gate oxide film 6 and the silicon gate electrode 7, the formation of the source region 8 and the drain region, and the silicon
The gate electrode 7 is made conductive, and the source electrode is connected to the bit line, the gate electrode to the word line, and the drain electrode to the precharge line. As can be seen from the above description, in the charge pumping memory according to the present invention, each memory cell is separated from each other by a buried insulating layer and a p/n junction, and the p/n junction is connected to a channel. Since it is formed only below the region, its area is small, and the leakage current per unit area of the p/n junction itself is small, similar to that of a bulk type MOS transistor, and the charge accumulated in the channel region is Retention time becomes longer. Further, compared to a bulk type MOS transistor, the junction area between the source and drain is smaller, and there is an advantage that it is easier to form a floating channel structure.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the main parts of one embodiment of the present invention, Figures 2 and 3
The figure is a process explanatory diagram for manufacturing the above embodiment. In the figure, 1 is a substrate, 2 is a semiconductor layer, 3 is a buried oxide layer, 4 is a single crystal semiconductor layer, 4' is a polycrystalline semiconductor layer, 5 is an isolation region, 6 is a gate oxide film, and 7 is silicon - A gate electrode, 8 is a source region, 9 is a drain region, S is a source electrode, D is a drain electrode, and G is a gate electrode. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 a one-conductivity type semiconductor region in a floating state;
a gate electrode provided on the region, and a source and drain region composed of opposite conductivity type semiconductor regions sandwiching the gate electrode and adjacent to the region, and the one conductivity type region In a memory device that achieves a memory function depending on the presence or absence of charge accumulation therein, the region of one conductivity type is disposed on a semiconductor substrate of an opposite conductivity type, and an insulator is provided adjacent to the region of the opposite conductivity type. A semiconductor memory device characterized by being surrounded by layers.