JPS6041468B2 - Manufacturing method of gate turn-off thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a gate turn-off thyristor (hereinafter referred to as GTO).

In general, switching elements such as GTO are required to have high switching speed and low heat loss.

In particular, power switching elements used in high-output inverters for railway choppers are required to have large current and high voltage resistance in addition to the above-mentioned characteristics in order to miniaturize the device and increase capacity. These performances are often determined by the internal configuration of the element, and there is a trade-off relationship between these performances. For example, increasing the withstand voltage requires widening the width of the intermediate layer that serves as the base layer, but increasing the width increases the on-voltage and increases heat loss, and furthermore, the volume of the intermediate layer increases, which increases the width of the intermediate layer that serves as the base layer. There is a trade-off relationship between performance, such that it takes time for excess carriers to disappear and the switching operation becomes slow. In practice, therefore, when obtaining a switching element with low power consumption, the trade-off point between each characteristic is optimized depending on the application. However, some device parameters are outside the trade-off relationship; for example, the higher the minority carrier lifetime in the semiconductor layer containing the control electrode, the higher the fin flow amplification factor of the transistor based on this layer. However, the switching performance is improved, the on-voltage is lowered, and the leakage current is also reduced, so that the device performance is almost improved.

Therefore, in a switching element, it is generally desirable to make the carrier lifetime of a semiconductor substrate as high as possible before diffusing lifetime killer atoms, such as gold (Au) atoms. However, in the actual manufacturing process, in order to introduce impurities into the semiconductor substrate, it is necessary to introduce impurities into the semiconductor substrate.
When heat treatment is performed at a high temperature of 100 yen or more, carrier trap levels are created by heavy metals mixed in from the container during the heat treatment and thermal strain caused in the semiconductor substrate by the heat treatment, reducing the carrier lifetime.

This phenomenon, unlike intentional lifetime control such as the diffusion of lifetime killer atoms, has been the main cause of deterioration of device performance and reproducibility of device manufacturing. The Ringetta method is well known as one of the solutions to this problem.

This is because a phosphorus compound is formed (deposited) on a semiconductor substrate, and when the phosphorus in the phosphorus compound is diffused into the semiconductor substrate, heavy metals such as Fe and Cu contained in the semiconductor substrate are diffused by heat, and the phosphorus in the phosphorus compound is diffused into the semiconductor substrate. This method takes advantage of the effect that heavy metals are adsorbed on the phosphorus compound layer of the semiconductor substrate, resulting in a decrease in the amount of heavy metals in the semiconductor substrate and an increase in lifetime. A method using this Ringetter effect will be specifically explained with reference to FIGS. 1a to 1d. What is shown in FIGS. 1A to 1D is an example of the manufacturing process of a thyristor, which is one of the switching elements. First, from both sides of the n-type Si substrate 11, for example, Ga
is diffused to form a p-type layer 12 that will become an anode layer, and a p-type layer 13 that will later become a p-base layer on which a gate electrode will be formed to obtain a Si substrate 11 with a p-n-p structure (see Fig. 1a). ). Next, a phosphorous glass layer 14 is formed (deposited) on the p-type layer 13 which will become the p-base layer (FIG. 1b). When this phosphorus glass layer 14 is formed, heavy metals contained in the Si substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14 . Thereafter, the phosphorus glass layer 14 is removed, and the phosphorus contained near the surface of the Si substrate 11 is diffused to form an n-type layer 15 that becomes a cathode layer (FIG. 1c). Note that the reason why phosphorus is diffused after removing the phosphorus glass layer 14 in this step is to control the surface concentration and depth of the n-type layer that will become the cathode layer. Thereafter, lifetime killer atoms (indicated by dots in the figure) are diffused from the side of the p-type layer 12, which will become the anode layer (FIG. 1d). Finally, although not shown, an anode electrode is provided on the p-type layer 12 which becomes an anode layer.
A thyristor element is obtained by forming a gate electrode on the P-type layer 13, which becomes a p-base layer, and a cathode electrode on the n-type layer 15, which becomes a cathode layer. Since the thyristor element obtained in this way utilizes the ring getter effect, the Si substrate 1
The amount of heavy metals in 1 is reduced and the life time is improved.

However, the improvement in lifetime is only slight, and as a result, it is almost the same as a method that does not utilize the Ringetter effect. A possible reason for this is that since the phosphorus glass layer 14 is not formed when phosphorus is diffused, heavy metals that have been sucked into the vicinity of the surface of the Si substrate 11 are re-diffused during the diffusion of phosphorus,
This is to infiltrate into 1. As described above, there was a fatal flaw in the manufacturing process in that while the lifetime was once increased during the formation (deposition) of the phosphorus glass layer, the carrier lifetime was lowered during the diffusion of phosphorus. The present invention was made in view of the above-mentioned drawbacks, and provides a method for manufacturing a switching element that has a high carrier lifetime and improved switching characteristics.

That is, the present invention diffuses phosphorus (n-type impurity) into a semiconductor substrate to form an n-type layer (n-emitter layer), then forms a layer containing phosphorus on the surface of the semiconductor substrate again, and lowers the n-type layer formation temperature. 900qo~1100q lower and higher than Au diffusion temperature
Perform ring etching at a temperature of o.

This is a CTO manufacturing method that once again improves the lifetime. An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 2a to 2f are cross-sectional views illustrating the manufacturing process of a GTO according to an embodiment of the present invention, which corresponds to FIG. 1. The steps a to c in FIG. 2 are the same as a to c in FIG. 1. That is, first, Ga is diffused from both sides of an n-type Si substrate 11 to form a p-type layer 12 which will become an anode layer, and a p-type layer 13 which will later form a gate electrode and a p-base layer to form a p-n-p structure. S
i A substrate 11 is obtained (FIG. 2a). Next, a phosphorus glass layer 14 is formed (deposited) on the p-type layer 13 which will become the p-base layer (FIG. 2b). At this time, p-type layer 1 which becomes an anode layer
Either the second side is covered with a Si02 film or the like, or the surface of the p-type layer 12, which will become the anode layer, is etched away during the subsequent process of removing phosphorus glass, and an n-type layer is formed on the surface of the p-type layer 12. Eliminate. When forming this phosphor glass layer 14, Si
Heavy metals contained in the substrate and heavy metals present outside are adsorbed to the phosphor glass layer 14. Therefore, in this step, the lifetime of the Si substrate, especially the p-type layer which becomes the p-base layer, is improved several tens of times as will be explained later. After that, the phosphorus glass layer 14 is removed,
Si substrate 1 The phosphorus contained in 1 is heated to 5 at a temperature of about 120,000
An n-type layer 15 which becomes a cathode layer is formed by diffusion for a certain period of time (FIG. 2c). In this process of diffusing phosphorus, the heavy metals that had been attracted near the surface of the Si substrate as described in the conventional example are removed by S
It is re-diffused into the i-substrate, and the lifetime of the Si substrate, particularly the p-type layer 13 which becomes the p-base layer, decreases and returns to its original value as will be explained later (FIG. 3). The process up to this point is the same as the conventional method, that is, the method shown in FIG. After this, the n-type layer 15, which will become the cathode layer, is divided into multiple parts 15a,
5b, 15c, 15d, and 15e have a suitable multi-emitter structure (FIG. 2d). The following step is an important step of the present invention. That is, after dividing the n-type layer 15 into a plurality of parts, the phosphor glass layer 26 is again formed on the surface of the divided n-type layer 15 (
Deposition) (Fig. 2e). POC13 is used as a source when forming the phosphor glass layer 26, and the temperature during the formation, that is, the ring getter temperature, is 100,000 &. In this way, the phosphorus glass layer 2
6, the lifetime, which had been lowered during the phosphorus diffusion process, is improved again, and as will be explained later (see Figure 3), the lifetime is improved several tens of times after the phosphorus diffusion process. After that, Au atoms (
(shown as dots in the figure) (Fig. 2 f). This Au atom diffusion process is carried out at a temperature of 80,000 °C for about 3 to 9 hours, but because the temperature is lower than the Ringetster temperature and the time is shorter (step c in Figure 2), there is little re-diffusion of heavy metals. .
Furthermore, it is not necessarily necessary to remove the phosphor glass layer 26 during this Au atom diffusion step. The reason for this is that, as explained above, the diffusion of Au atoms is lower than the ring getter temperature and for a short time, so phosphorus does not diffuse and the initial impurity (phosphorus) concentration is maintained and the depth hardly changes. Because they don't. Finally, although not shown, as in the conventional example, an anode electrode is formed on the p-type layer 12 that becomes the anode layer, a gate electrode is formed on the p-type layer 13 that becomes the p-base layer, and a cathode electrode is formed on the n-type layer 15 that becomes the cathode layer. A gate turn-off thyristor element is obtained. The gate turn-off thyristor element thus obtained has a longer lifetime of the Si substrate, particularly the p-type layer serving as the p-base layer, and has better switching characteristics than a subordinate gate turn-off thyristor element.

Next, the p-type layer 13 which becomes the Si substrate, ie, the p-base layer, of the gate turn-off silicate element obtained as in the above embodiment is prepared.
The lifetime of the p-type layer 13, which is the p-base layer of the conventional gate turn-off thyristor element, is
How good it is will be specifically explained with reference to FIG.

In FIG. 3, the dotted line indicates the subordinate column, the solid line indicates the embodiment of the present invention, and a
is when the p-type layer is formed, b is when the first phosphorus glass layer is formed,
c is when phosphorus diffuses, e is when the second phosphorus glass layer is formed (
In one embodiment of the present invention only), f is a curve diagram showing the lifetime (msec) of the n-type layer 11 which becomes the n-base layer of the gate turn-off thyristor element when gold is diffused. This third
As is clear from the figure, in the case of a secondary structure, the lifetime of the n-type layer, which is the n-base layer of the Si substrate, is 0.6 to 1.1 peaks.
On the other hand, in the case of one embodiment of the present invention, the lifetime of the n-type layer is about 1.1 to 1.3 sec. It was rank. In other words, in the case of a subordinate, the target value is 1.2 sec. There were many things that I had never seen before, and there were large variations. On the other hand, in the case of one embodiment of the present invention, the target value was almost reached and there was little variation. In this way, the lifetime almost reaches the target value and there is little variation (good reproducibility)
The reason for this is that the phosphorus glass layer 26 is formed (deposited) again after phosphorus is diffused as described above. That is, by depositing the phosphorus glass layer 26 after diffusing phosphorus, the heavy metals rediffused into the Si substrate and external heavy metals are adsorbed again to the phosphorus glass layer 26, and then gold diffusion is performed at a temperature of about 80,000°C. This is because even if the phosphorus is applied, the amount of heavy metals in the Si substrate immediately after phosphorus is diffused will be reduced. Note that the lifetime measurement in FIG. 3 was carried out by the diode voltage drop method, and what is shown in FIG. 3 is the change in lifetime when more than 90,000 heat treatment steps were performed. In this way, the lifetime of the n-type layer, which becomes the n-base layer, is almost the target value, but the p
Unfortunately, there is currently no means to directly measure the lifetime of the p-type layer 13, which serves as the base layer, but it can be sufficiently determined by calculating it from the lifetime of the n-type layer or by inferring it from the device characteristics. The commonly used calculation formula is 7PB(n) = state BNC poison, TPB(X) is p
7NB is the lifetime of the n-type layer 11, CN8 is the impurity concentration of the n-type layer 11, and CPB(x) is the impurity concentration that is a function of the depth of the p-type layer 13. are represented respectively.

It can be easily estimated if the average life size of the p-type layer is 7PB to BN.

Here, CPB is the average impurity concentration of the p-type layer. The sample used in the experiment shown in Figure 3 is CNB = 4 x 1 and 3 skin - 3
,CPB=4×1bi7skin-3, so ↑pB=↑NB
/100, so if the lifetime of the n-type layer shown in FIG. 3 is reduced to 1/100, the lifetime of the p-type layer can be obtained.

However, the above relational expression cannot be used for the lifetime in the gold diffusion process, and the lifetime of the n-type layer in which gold is selectively diffused is lower than that in the previous process, but the p-type layer, which is hardly affected by gold diffusion, is The lifetime of the mold layer will maintain most of the values from the previous process. According to FIG. 3, therefore, the p-type layer lifetime of the present invention is about 4 tones louder than the conventional one.

Note that deposition of 900 OO or more using POC13 or the like as a diffusion source is effective in forming the phosphorus glass layer. Formation of phosphorus glass by CVD is usually performed at a temperature of about 500°C, but the diffusion constant of copper (C), iron (Fe), and gold (Au), which are the main contaminating heavy metals in semiconductors, is 50°C.
At 0℃, Cu and Fe are 6×10-9/sec,
900qo is 10-6/sec, Au is 50020
10-7 at 900 pm for 10-11/sec at
/sec, 90000 is 2 to 4 digits larger in both cases. This is important in the ring getter process which is a part of the present invention; the higher the temperature, the more the diffusion of heavy metals will be promoted, and the heavy metals in the semiconductor will be adsorbed into the phosphor glass layer. However, if the temperature is too high, phosphorus will diffuse into the semi-dynamic body and change the impurity concentration distribution, so the temperature for forming the phosphorus glass layer of the present invention is preferably in the range of 900 to 1100°C. The formation temperature of this phosphorus glass layer is 0, and the phosphor getter temperature is 4th.
It can be seen from the experimental facts shown in the figure that a temperature of 900° C. to 1100 qo is good. This figure 4 shows the change in lifetime (vertical axis) with respect to the ring getter temperature (horizontal axis).
It can be seen that the lifetime is high and its variation is small depending on the temperature, and it is also understood that the lifetime does not necessarily improve as the temperature of the ring getter increases.
Furthermore, crystal defects in the silicon substrate are reduced by the annealing effect at the same time that the above-mentioned IJ glass layer forming temperature is applied to the silicon substrate. For example, 1000℃
After heating for about 1 hour, crystal defects are reduced to about 1/3 of the amount before heating.
It decreases to ~1/4 and the lifetime increases accordingly.
The maximum heating temperature for glass formation by CVD is 600°C.
The annealing effect is almost negligible. By implementing the present invention as described above, various characteristics were improved as follows compared to the conventional GTO.

Gate turn-off current 600A, anode current 60V GT
The on-voltage of O is increased from 3.3V to 2.2V, the surge current capacity is increased from 300 to 500M, and the latching current is increased to 10A.
The off-voltage has been improved from 1500V to 3000V. Further, in the method of the present invention, some heat treatment process such as a thermal oxidation process, a p-type diffusion process, a CVD process, etc. may be interposed between the n-type layer plurality division process and the getter process.

[Brief explanation of drawings]

1A to 1D are process cross-sectional views for explaining a conventional method for manufacturing a switching element, FIGS. 2A to 2F are process cross-sectional views for explaining an embodiment of the present invention, and FIG. FIG. 1 is a curve diagram showing a comparison of lifetimes corresponding to the manufacturing process, and FIG. 4 is a curve diagram for explaining the effects of the present invention. 11: n-type Si substrate, 11: Si substrate, 12: p-type layer to become an anode layer, 13: p-type layer to become p-base layer, 14
and 26: phosphorus glass layer, 15: n-type layer which becomes a cathode layer. Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] 1. Diffusing p-type impurities from both sides of an n-type semiconductor substrate to
n on the surface of one p-type layer formed in the process of forming a type layer.
a step of forming a layer containing a type impurity; a step of performing heat treatment after the step to diffuse the n-type impurity to form an n-type layer; and a step of dividing the n-type layer obtained by the step into a plurality of layers. , a method for manufacturing a gate turn-off thyristor comprising the step of diffusing lifetime killer atoms from the surface of the p-type layer on which the n-type layer is not formed, the step of dividing the n-type layer into a plurality of parts; Between the step of diffusing atoms, a layer containing phosphorus is formed on the surface of the n-type layer divided into a plurality of parts, and the temperature is lower than the n-type layer formation temperature and higher than the lifetime killer atom diffusion temperature.
1. A method for manufacturing a gate turn-off thyristor, characterized in that ringettering is performed at a temperature of 0°C to 1100°C. 2. The method for manufacturing a gate turn-off thyristor according to claim 1, wherein the layer containing phosphorus is formed using POCl_3 as a diffusion source. 3. The method for manufacturing a gate turn-off thyristor according to claim 1, characterized in that the layer containing phosphorus formed on at least one surface of the semiconductor substrate is formed using POCl_3 as a diffusion source.