JPS6119104B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention applies to individual elements such as transistors and thyristors, or bipolar integrated circuits (hereinafter referred to as bipolar integrated circuits).
This invention relates to a method for manufacturing semiconductor devices such as ICs. Generally, semiconductor devices such as transistors, thyristors, and bipolar ICs are required to have high speed, high gain, and low heat loss. In particular, individual elements are required to have high current and high voltage resistance in addition to the above-mentioned performance in order to miniaturize and increase capacity of applied devices. These performances are often determined by the internal configuration of the element, and there is a trade-off relationship between these performances. For example, to improve high speed, it is necessary to lower the lifetime of the neutral region and reduce the thickness of each semiconductor layer, but lowering the lifetime reduces current gain, increases on-state voltage, and causes heat loss. There is a trade-off relationship between the performances, such as an increase in the semiconductor layer thickness, and a reduction in the thickness of the semiconductor layer makes it impossible to obtain a high breakdown voltage. In fact, the trade-off point between each characteristic of a semiconductor device is optimized depending on the application. However, some device parameters are outside the trade-off relationship; for example, the higher the minority carrier lifetime in the semiconductor layer containing the control electrode, the higher the current amplification factor of the transistor based on this layer. , the switching performance is improved, the on-voltage is lowered, and the leakage current is also reduced, so that the device performance is almost improved. Therefore, in semiconductor devices such as individual devices or bipolar ICs, it is generally desirable to make the carrier lifetime of the semiconductor substrate as high as possible. However, in the actual manufacturing process, high-temperature heat treatment of over 1000℃ such as diffusion is performed to introduce impurities into the semiconductor substrate. The resulting thermal strain creates a carrier trap level, reducing the carrier lifetime. This phenomenon, unlike intentional lifetime control such as the diffusion of lifetime killer atoms, has been a major cause of deterioration of device performance and reproducibility of device manufacturing. The Ringetter method is well known as one of the solutions to this problem. This is because a phosphorus compound is formed (deposited) on a semiconductor substrate, and when the phosphorus in the phosphorus compound is diffused into the semiconductor substrate, heavy metals such as Fe and Cu contained in the semiconductor substrate are diffused by heat, and the semiconductor substrate is heated. This takes advantage of the effect that heavy metals are adsorbed on the upper phosphorus compound layer, resulting in a reduction in heavy metals in the semiconductor substrate and a longer lifetime. A method using this Ringetter effect will be specifically explained with reference to FIGS. 1a to 1d.
What is shown in FIGS. 1a to 1d is an example of the manufacturing process of a thyristor, which is one of the individual elements. First, for example, Ga is diffused from both sides of an n-type Si substrate 11 to form a p-type layer 12 that will become an anode layer, and later a gate electrode is formed.
A p-type layer 13 serving as a base layer is formed to form a p-n-
A p-structure Si substrate 11 is obtained (FIG. 1a). Then p
A phosphorus glass layer 14 is formed on the p-type layer 13 serving as a base layer.
(deposition) (FIG. 1b). When this phosphorus glass layer 14 is formed, heavy metals contained in the Si substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14 . Thereafter, the phosphorus glass layer 14 is removed, and phosphorus contained near the surface of the Si substrate 11 is diffused to form an n-type layer 15 that will become a cathode layer (FIG. 1c). Note that the reason why phosphorus is diffused after removing the phosphorus glass layer 14 in this step is to control the surface concentration and depth of the n-type layer that will become the cathode layer. Thereafter, lifetime killer atoms (indicated by dots in the figure) are diffused from the side of the p-type layer 12, which will become the anode layer (FIG. 1d).
Finally, although not shown, the p layer 1 becomes the anode layer.
2 has an anode electrode and a p-type layer 13 which becomes a p base layer.
A thyristor element is obtained by forming a gate electrode and a cathode electrode on the n-type layer 15 which becomes a cathode layer. Since the thyristor element obtained in this way utilizes the Ringetter effect, the Si substrate 11
The amount of heavy metals inside is reduced and the life time is improved. However, the improvement in lifetime is due to
The amount is small, and as a result, it is almost the same as a thyristor using a method that does not use the Ringetter effect. A possible reason for this is that the phosphorus glass layer 14 is not formed when phosphorus is diffused, so the heavy metals attracted near the surface of the Si substrate 11 are
This is because when phosphorus is diffused, it is re-diffused and penetrates into the Si substrate 11. As described above, there was a fatal flaw in the manufacturing process in that while the lifetime was once increased during the formation (deposition) of the phosphorus glass layer, the carrier lifetime was lowered during the diffusion of phosphorus. The present invention was made in view of the above-mentioned drawbacks.
The present invention provides a method for manufacturing a semiconductor device with a high carrier lifetime and improved various characteristics. That is, the present invention diffuses phosphorus (n-type impurity) into a semiconductor substrate, and then forms a thin film having a thickness that allows phosphorus to pass through at least one surface of the semiconductor substrate and prevents phosphorus from being diffused into the semiconductor substrate. In this method, the semiconductor substrate is then heat-treated in an atmosphere containing phosphorus to improve the lifetime again. An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2e show an embodiment of the present invention,
FIG. 2 is a process cross-sectional view showing the manufacturing process of the thyristor corresponding to FIG. 1; The steps a to c in FIG. 2 are the same as a to c in FIG. 1. That is, first, Ga is diffused from both sides of an n-type Si substrate 11 to form a p-type layer 12 that will become an anode layer, and a p-type layer 13 that will later become a p-base layer on which a gate electrode will be formed. Structure of Si
A substrate 11 is obtained (FIG. 2a). Next, a phosphorus glass layer 14 is formed (deposited) on the p-type layer 13, which becomes the p-base layer (FIG. 2b). At this time, the p-type layer 12 side, which normally becomes the anode layer, is not shown.
Cover with SiO ₂ film, etc. This phosphorus glass layer 1
4, heavy metals contained in the Si substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14. Therefore, in this step, the lifetime of the Si substrate, especially the p-type layer which becomes the p-base layer, is improved several tens of times as will be explained later. After that, the phosphor glass layer 14 is removed, and the Si substrate 1 is
Phosphorus contained in 1 is diffused at a temperature of about 1200°C for about 5 hours to form an n-type layer 15 that will become a cathode layer (second
Figure c). In this step of diffusing phosphorus, as mentioned in the conventional example, the heavy metals that have been attracted near the surface of the Si substrate are re-diffused into the Si substrate, and the life tom of the Si substrate, especially the p-type layer 13 which becomes the p-base layer, is reduced. As will be explained later (FIG. 5), it returns to its original value.
The process up to this point is the same as the conventional method, that is, the method shown in FIG. The following step is an important step of the present invention. That is, after phosphorus is diffused into the p-type layer 13 of the Si substrate, which becomes the so-called p-base layer, a thermal oxide film 26 having a thickness that allows phosphorus to pass through and prevents phosphorus from being diffused into the substrate is applied to the p-type layer 12, which becomes the anode layer. This is a step of forming a substrate and heat-treating it in an atmosphere containing phosphorus (FIG. 2d). For example, a thermal oxide film 26 of 5000 Å is formed in an atmosphere containing phosphorus.
Heat treatment is performed at 1000°C for 1 hour. Here, the thermal oxide film is formed only on the p-type layer 12 which becomes the anode layer, but there is of course no problem in forming it on the n-type layer 15 which becomes the cathode layer. For example, in a semiconductor device such as a planar type device in which a p-type layer is exposed on the surface, a thermal oxide film should be formed on both surfaces to prevent phosphorus from diffusing into the semiconductor substrate. When the silicon substrate 11 is treated in an atmosphere containing phosphorus in this way, the lifetime, which had been lowered due to the phosphorus diffusion process, is improved again, and as will be explained later (Figure 5), the lifetime is improved by several tens of times immediately after the phosphorus diffusion process. do. Thereafter, the thermal oxide film 26 is removed, and Au atoms (indicated by dots in the figure), which are lifetime killer atoms, are diffused from the p-type layer 12 side, which will become the anode layer, in the same manner as in the step of FIG. 1d. Finally, although not shown, as in the conventional example, an anode electrode is formed on the p-type layer 12 that becomes the anode layer, a gate electrode is formed on the p-type layer 13 that becomes the p-base layer, and a cathode electrode is formed on the n-type layer 15 that becomes the cathode layer. As a result, a thyristor element can be obtained. FIGS. 3a to 3e are process sectional views showing other embodiments of the present invention and showing the manufacturing process of a thyristor corresponding to FIG. 1. The steps a to c in FIG. 3 are the same as a to c in FIG. 1. That is, first, Ga is diffused from both sides of an n-type Si substrate 11 to form a p-type layer 12 that will become an anode layer, and a p-type layer 13 that will later become a p-base layer on which a gate electrode will be formed to form a p-n-p structure. A Si substrate 11 of (FIG. 3a) is obtained. Next, a phosphorus glass layer 14 is formed (deposited) on the p-type layer 13, which becomes the p-base layer (FIG. 3b). At this time, the p-type layer 12 side, which normally becomes the anode layer, is not shown.
Cover with SiO ₂ film, etc. This phosphorus glass layer 1
4, heavy metals contained in the Si substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14. Therefore, in this step, the lifetime of the Si substrate, especially the p-type layer which becomes the p-base layer, is improved several tens of times as will be explained later. After that, the phosphor glass layer 14 is removed, and the Si substrate 1 is
Phosphorus contained in 1 is diffused at a temperature of about 1200°C for about 5 hours to form an n-type layer 15 that will become a cathode layer (3rd layer).
Figure c). In this step of diffusing phosphorus, as mentioned in the conventional example, the heavy metals that were attracted near the surface of the Si substrate are re-diffused into the Si substrate, reducing the lifetime of the Si substrate, especially the p-type layer 13 which becomes the p-base layer. , it returns to its original value as will be explained later (FIG. 5). The process up to this point is the same as the conventional method, that is, the method shown in FIG. The following step is an important step of the present invention. In other words, a p-type layer 13 that becomes a so-called p base layer with phosphorus as a Si substrate.
This is a step of forming a low-temperature oxide film 37 on the p-type layer 12, which will become the anode layer, and having a thickness that allows phosphorus to pass through and prevents phosphorus from being diffused into the substrate, and then heat-treating this in an atmosphere containing phosphorus ( Figure 3 d).
For example, the low temperature oxide film 37 is formed using CVD method etc.
A film with a thickness of 5000 Å is formed and heat treated at 1000° C. for 1 hour in an atmosphere containing phosphorus. Here, the low-temperature oxide film is formed only on the p-type layer 12, which becomes the anode layer, but there is, of course, no problem in forming it on the n-type layer 15, which becomes the cathode layer. In a semiconductor device in which a mold layer is exposed, a low-temperature oxide film should be formed on both sides in order to prevent phosphorus from diffusing into the semiconductor substrate. When the silicon substrate 11 is treated in an atmosphere containing phosphorus in this way, the lifetime, which had decreased due to the phosphorus diffusion process, is improved again, as will be explained later (FIG. 5).
As a result, the improvement is several tens of times higher than that immediately after phosphorus diffusion. Thereafter, the low-temperature oxide film 37 is removed, and Au atoms (indicated by dots in the figure), which are lifetime killer atoms, are diffused from the p-type layer 12 side, which will become the anode layer, in the same manner as in the step shown in FIG. 1d. Finally, although not shown, as in the conventional example, an anode electrode is placed on the p-type layer 12 that becomes an anode layer, a gate electrode is placed on the p-type layer 13 that becomes a p-base layer,
A thyristor element is obtained by forming a cathode electrode on the n-type layer 15 serving as a cathode layer. FIGS. 4a to 4e show other embodiments of the present invention,
FIG. 2 is a process cross-sectional view showing the manufacturing process of the thyristor corresponding to FIG. 1; Items a to c in FIG. 4 are the same as a to c in FIG. 1. That is, first, the n-type Si substrate 11
Ga is diffused from both sides to form a p-type layer 12 that will become an anode layer, and a p-type layer 13 that will later become a p-base layer on which a gate electrode will be formed.
A substrate 11 is obtained (FIG. 4a). Next, a phosphorus glass layer 14 is formed (deposited) on the p-type layer 13, which will become the p-base layer (FIG. 4b).At this time, the p-type layer 12 side, which will become the anode layer, is usually SiO ₂ (not shown).
Cover with a membrane, etc. When this phosphorus glass layer 14 is formed, heavy metals contained in the Si substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14 . Therefore, in this step, the lifetime of the Si substrate, especially the p-type layer which becomes the p-base layer, is improved several tens of times as will be explained later. Thereafter, the phosphorus glass layer 14 is removed, and the phosphorus contained in the Si substrate 11 is diffused at a temperature of about 1200° C. for about 5 hours to form an n-type layer 15 that will become a cathode layer (FIG. 4c).
In the process of diffusing this phosphorus, as described in the conventional example,
The heavy metals that had been attracted near the surface of the Si substrate are re-diffused into the Si substrate, and the P
The lifetime of the mold layer 13 decreases and returns to its original value as will be explained later (FIG. 3). The process up to this point is the same as the conventional method, that is, the method shown in FIG. The next step is an important step of the present invention. That is, phosphorus is Si
After diffusing into the p-type layer 13 which will become the so-called p-base layer of the substrate, a polycrystalline silicon film 48 having a thickness that allows phosphorus to pass therethrough and prevents phosphorus from being diffused into the substrate is formed on the p-type layer 12 which will become the anode layer. This is a process of heat-treating the material in an atmosphere containing phosphorus (Fig. 2d). Although it is assumed here that the polycrystalline silicon film is formed only on the p-type layer 12 that will become the anode layer, there is of course no problem in forming it on the n-type layer 15 that will become the cathode layer. Naturally, in a semiconductor device in which the p-type layer is exposed, polycrystalline silicon films should be formed on both sides in order to prevent phosphorus from diffusing into the semiconductor substrate. When the silicon substrate 11 is treated in an atmosphere containing phosphorus in this way, the lifetime, which had been lowered during the phosphorus diffusion process, is improved again, and as will be explained later (Figure 3), it is improved by several tens of times immediately after the phosphorus diffusion. . After that, the polycrystalline silicon film 48 is removed, and Au atoms (indicated by dots in the figure), which are lifetime killer atoms, are added from the p-type layer 12 side, which will become the anode layer, in the same manner as in the step d in FIG.
to spread. Finally, although not shown, an anode electrode is provided on the p-type layer 12 which becomes an anode layer as in the conventional example.
A thyristor element is obtained by forming a gate electrode on the p-type layer 13 serving as a p-base layer and forming a cathode electrode on the n-type layer 15 serving as a cathode layer. The thyristor element thus obtained is different from the conventional thyristor element obtained as shown in FIGS.
The mold layer has a long lifetime and good switching characteristics. Next, the lifetime of the p-type layer 13 which becomes the Si substrate, that is, the p base layer, of the thyristor element obtained as in the above example is compared with the lifetime of the p-type layer 13 which becomes the Si substrate, that is, the p base layer, of the thyristor element obtained in the conventional manner, that is, as shown in FIGS. p to be the base layer
How good the lifetime of the mold layer 13 is is specifically explained using the example shown in FIG. 2 with reference to FIG. 5. This figure 5 is different from the conventional figure 1 a.
- d and corresponding to Figs. 2 a to e of one embodiment of the present invention.
Lifetime (μsec) of the n-type layer 11 which becomes the n-base layer of the thyristor element for a′ to d′, a″ to e″
In this curve diagram, the dotted line is for the conventional case, and the solid line is for the embodiment of the present invention. As is clear from FIG. 5, in the conventional case, the life time of the n-type layer which is the n-base layer of the Si substrate is about 0.6 to 1.1 μsec, while in the case of the embodiment of the present invention, the life time of the n-type layer is about 0.6 to 1.1 μsec. The lifetime was about 1.1 to 1.3 μsec. That is, in the conventional case, there were many cases where the target value of 1.2 μsec. was not met, and the variation was large. On the other hand, in the case of one embodiment of the present invention, the target value was almost achieved and there was little variation. The reason why the lifetime almost achieved the target value and had little variation (good reproducibility) is that the silicon semiconductor substrate 11, which was masked with a thin film that transmits phosphorus again after diffusing phosphorus, as described above, By heat treatment in an atmosphere containing phosphorus, Si
The heavy metals re-diffused into the substrate and the external heavy metals are again adsorbed by the phosphorus in the atmosphere, and after this
This is because even if gold diffusion is performed at a temperature of about 850°C, the amount of heavy metals in the Si substrate will be reduced immediately after phosphorus is diffused. The measurement of lifetime in FIG. 5 was carried out by the diode voltage drop method, and what is shown in FIG. 5 is the change in lifetime when a heat treatment step of 700° C. was performed. In this way, the lifetime of the n-type layer, which becomes the n-base layer, is almost the target value, but unfortunately there is currently no means to directly measure the lifetime of the p-type layer 13, which becomes the p-base layer. This can be sufficiently determined by calculating the lifetime of the layer or by analogy with the device characteristics. Frequently used calculation formulas are

In [Formula], τ _PB(X) is the lifetime which is a function of the depth of the p-type layer, and τ _NB is the lifetime of the n-type layer 1
1, _CNB represents the impurity concentration of the n-type layer 11, and CPB _(X) represents the impurity concentration as a function of the depth of the p-type layer 13, respectively. The average lifetime _PB of the p-type layer is

It can be easily estimated using [Formula]. Here, _PB is the average impurity of the p-type layer. The sample used in the experiment shown in Figure 5 was C _NB =4×
10 ¹³ cm ^-3・_PB = 4×10 ¹⁷ cm ^-3 , so _PB =
Since τ _NB /100, the lifetime of the p-type layer can be obtained by reducing the lifetime of the n-type layer shown in FIG. 5 to 1/100. However, the above relational expression cannot be used for the lifetime in the gold diffusion process, and the lifetime of the n-type layer in which gold is selectively diffused is lower than that in the previous process, but the p-type layer, which is hardly affected by gold diffusion, is As for the lifetime of the mold layer, most of the values from the previous process are maintained. Therefore, according to FIG. 5, the p-type layer lifetime of the present invention is about 40 times longer than that of the conventional example. In addition, the heat treatment temperature in the atmosphere containing phosphorus in the present invention is 700-1200, considering the getter effect of phosphorus.
A range of ℃ is suitable. Figure 6 shows the forward blocking characteristics of the thyristor in the conventional a
FIG. 7 shows a comparison of the forward conduction characteristics between conventional a and one embodiment of the present invention. From FIG. 6, it can be seen that the forward blocking voltage of the method according to the embodiment of the present invention is approximately twice as high as that of the conventional method (FIG. 1), and from FIG. It can be seen that the on-voltage is reduced by about 1/2. As explained above, according to the present invention, the switching characteristics (temporal) are slightly improved (when multiple devices are connected in parallel, the above-mentioned effects are obtained), and it is possible to increase the withstand voltage and reduce heat loss. Furthermore, reproducibility and control range in the manufacturing process are improved. The above explanation has been made using the embodiment shown in FIG.
The same applies to the embodiments shown in FIGS. Although the method of the present invention was applied to a thyristor in the above embodiment, it can also be applied to solid elements such as transistors, GTOs, or optical thyristors, as well as bipolar devices.
Of course, it can be applied to bipolar semiconductor devices such as ICs. In addition, in the above examples, only typical heat treatment steps before gold diffusion were considered;
In the method of the present invention, even if some heat treatment process such as a thermal oxidation process, a p-type diffusion process, or a CVD process is interposed between the phosphorus diffusion process and the lifetime killer diffusion process, the effects of the present invention are not impaired. do not have. Further, in the above embodiments, the present invention is applied to a thyristor with gold diffusion, but the present invention can be similarly applied to a bipolar semiconductor element without gold diffusion.

[Brief explanation of the drawing]

Figures 1 a to d are process cross-sectional views for explaining a conventional method of manufacturing a switching element, and Figures 2 a to e
3A-3E and 4A-E are process sectional views for explaining another embodiment of the present invention, and FIG. 5 is a process sectional view for explaining another embodiment of the present invention. FIG. 6 is a curve diagram showing a comparison of changes in lifetime corresponding to the manufacturing process shown in FIG. 1 and changes in lifetime corresponding to the manufacturing process shown in FIG. A diagram comparing the forward blocking characteristic b of ) and the forward blocking characteristic a of the conventional (Fig. 1),
FIG. 7 is a diagram comparing the forward conduction characteristics of an embodiment of the present invention (FIG. 2) with the forward conduction characteristics of the conventional device (FIG. 1). 11... n-type Si substrate, 11... Si substrate, 12...
... p-type layer which becomes an anode layer, 13 ... p-type layer which becomes p base layer, 14 ... phosphorus glass layer, 15 ...
n-type layer serving as a cathode layer, 26...thermal oxide film, 3
7...Low temperature oxide film, 48...Polycrystalline silicon film.

Claims (1)

[Claims] 1. A step of forming a thin film on at least one surface of a semiconductor substrate having at least one pn junction to a thickness that allows phosphorus to pass therethrough and prevents phosphorus from being diffused into the substrate, and 1. A method for manufacturing a semiconductor device, comprising the steps of heat-treating both sides of a semiconductor substrate in an atmosphere containing phosphorus, and removing part or all of the thin film after the step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film formed on at least one surface of the semiconductor substrate is a thermal oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film formed on at least one surface of the semiconductor substrate is a low-temperature oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film formed on at least one surface of the semiconductor substrate is a polycrystalline silicon film. 5 The temperature of the phosphorus heat treatment step is 700 to 1200°C
A method for manufacturing a semiconductor device according to claim 1, characterized in that: