JPS6041740B2 - Level difference detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides level difference detection for detecting whether the ratio between the maximum signal level among a plurality of fluctuating signal levels and the individual signal levels is less than or equal to a predetermined value. Regarding circuits.

In a conventional level difference detection circuit of this type, two input signals are amplified separately by two multiplier amplifiers (or N°C amplifiers), and two input signals are amplified by two multiplier amplifiers (or M°C amplifiers). drawer)
The noise level in the output signal was compared, and the signal level was detected based on the noise level.

That is, the output signal level of the limiter amplifier (or M°C amplifier) is held constant, but when the input signal is large, the gain of the limiter amplifier (or AGC amplifier) is low; Therefore, the noise level is also low. If the input level is small, Λ゛-゛, 1 1.1゛ payment, 11-゛, 1j fumi l,)
The level can be detected by detecting the noise level using the L-meter. In the above detection method, noise outside the signal band is extracted in order to separate the noise component and the signal component. An example of a conventional level difference detection circuit is shown in FIG.

An example of a conventional level difference detection circuit will be explained based on FIG. 1. Out-of-band noise of input signals from terminals 1a and 2a is extracted by band-pass filters 11 and 12, amplified by high-frequency amplifier circuits 13 and 14, and alternately switched by tie auto switch 15 in synchronization with 5KH2. , M° C. amplifier 16 amplifies the signal to a certain level. This is detected by the envelope detection circuit 17, and the video amplification circuit 1
8 and amplified, the synchronous detection circuit 19 performs synchronous detection to obtain a DC voltage proportional to the S/N difference between the signal levels at the input terminals 1a and 2a, and the logic IC circuit 20 detects the level difference. . A 5KH2 synchronization signal is supplied from the pulse generation circuit 21 to the diode switch 15 and the synchronous detection circuit 19. (n) As configured above, the conventional level difference detection circuit extracts out-of-band noise, so as the signal bandwidth changes, the noise extraction frequency must be changed, and the noise extraction frequency must be changed. , since it is necessary to perform envelope detection, it has the disadvantage 7 that the amount of amplification by the amplifier increases.

Also, a synchronous detection circuit 19, a 5KH2 pulse generation circuit 21,
Since the logic 1C circuit 20 and the like are also required, the circuit has the disadvantage of being complicated and expensive. An object of the present invention is to provide a level difference detection circuit that eliminates the above-mentioned drawbacks and easily detects level differences by directly comparing signal levels, unlike conventional circuits.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a system diagram of an embodiment of the present invention, in which input signals from input terminals 1a and 2a are supplied to variable gain circuits 31 and 32, respectively.

The outputs of the variable gain circuits 31 and 32 are supplied to control voltage extraction circuits 35 and 36, respectively, which generate control voltages according to the outputs of the variable gain circuits. Furthermore, variable gain circuits 31 and 32
The outputs of are sent to output level detection circuits 33 and 34, respectively, and when the output of the variable gain circuit becomes smaller than a predetermined level, a detection signal is output to output terminals 1b and 2b. The control voltages are supplied to the control voltage selection circuits 37 of the control voltage extraction circuits 35 and 36, and only one of the control voltages is selected and supplied to the variable gain circuits 31 and 32. In this selection, a control voltage is selected that makes the gain smaller than the gain of the variable gain circuit. Further, the control voltage versus gain characteristics of the variable gain circuits 31 and 32 are made equal. With the configuration shown in FIG. 2, the control voltage extraction circuit 35
If the output is fed back to the variable gain circuit 31 without passing through the control voltage selection circuit 37, the output of the variable gain circuit 31 can be kept constant regardless of the level of the input signal supplied to the terminal 1a.

Similarly, control voltage extraction time. If the output of the line 36 is directly fed back to the variable gain circuit 32, the output of the variable gain circuit 32 can be kept constant regardless of the level of the input signal from the terminal 2a. When the gain control of the variable gain circuits 31 and 32 is performed using the outputs of the control voltage extraction circuits 35 and 36, respectively, . "The outputs of the variable gain circuits 31 and 32 are maintained at the same ACV", and the difference in signal level from the terminals 1a and 2a to be detected is set to DCdB], and the output of the variable gain circuits 31 and 3 is maintained at the same ACV.
It is assumed that when the level of the output of the circuit 2 becomes lower than ACV by DCdB, the level detection circuits 33 and 34 output a detection signal. Here, the control voltage selection circuit 37
The voltage at which the gain of the variable gain circuit becomes smaller is selected. Now, if the level of the input signal from the input terminal 1a is higher than the level of the input signal from the input terminal 2a, the control voltage selection circuit 37 selects the control voltage from the control voltage extraction circuit 35.

Therefore, the output level of the variable gain circuit 31 is A [■]
However, the output of the variable gain circuit 32 receiving the same control voltage becomes smaller than A[■]. At this time, if the output of the variable gain circuit 32 is smaller than ACV by D[B] or more, the output level detection circuit 34 outputs a false detection signal. Further, when the level of the input signal from the input terminal 2a is higher than the input signal from the input terminal 1a, the control voltage selection circuit 37 selects the control voltage from the control voltage extraction circuit 36. Therefore, the output of the variable gain circuit 32 is A [■]
As a result, the output of the variable gain circuit 31 becomes smaller than A [■], and the reduction width is DCd smaller than A [■].
B] If it is above, the output level detection circuit 33 outputs a detection signal. As explained in detail above, according to the present invention, even if the levels of the respective input signals input from the input terminals 1a and 2a vary, it is always checked whether the level difference exceeds D[B]. This can be determined from the detection signals of the output level detection circuits 33 and 34.

Although the first embodiment of the present invention detects the level difference between two signals, it is also possible to compare three or more signals. Figure 3 shows a case where there are three or more input terminals 1a, 2a.
..., Nal gain variable circuit 31, 32,...41
, output level detection circuits 33, 34, . . . , 42, control voltage extraction circuits 35, 36, . . . 43, and control voltage selection circuit 38. There are N input signals, and the operation is the same as in the case of FIG.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional level detection circuit, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. In the figure, 1a, 2a, Na...input terminals,
1b, 2b, Nb... Output terminal, 11, 12.
... Bandpass filter for noise extraction, 13, 14 ... High frequency amplifier circuit, 15 ... Diode switch circuit, 16 ... AGC amplification circuit, 17 ...
Envelope line detection circuit, 18... Video amplification circuit, 1
9...Synchronous detection circuit, 20...Logic 1C circuit, 21...5KHz synchronous generation circuit, 31, 32
, 41... variable gain circuit, 33, 34, 42...
...Output level detection circuit, 35, 36, 43...
. . . Control voltage extraction circuit, 37, 38 . . . Control voltage selection circuit.

Claims (1)

[Claims] 1. A plurality of variable gain circuits, a plurality of control voltage extraction circuits that output control voltages for controlling the gains of the plurality of variable gain circuits and keeping the output constant, and an output level of the plurality of variable gain circuits. multiple detection circuits that detect
A level difference detection circuit comprising: a control voltage selection circuit that selects one output from the outputs of the plurality of control voltage extraction circuits and supplies it to the plurality of variable gain circuits.