JPS6041870B2 - Method for manufacturing complementary MOS integrated circuit device - Google Patents
Method for manufacturing complementary MOS integrated circuit deviceInfo
- Publication number
- JPS6041870B2 JPS6041870B2 JP53015196A JP1519678A JPS6041870B2 JP S6041870 B2 JPS6041870 B2 JP S6041870B2 JP 53015196 A JP53015196 A JP 53015196A JP 1519678 A JP1519678 A JP 1519678A JP S6041870 B2 JPS6041870 B2 JP S6041870B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- complementary mos
- circuit device
- channel
- mos integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はＰチャンネル及びＮチャンネルＭＯＳ電界効果
トランジスタを構成要素とする相補型■４０５集積回路
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a complementary type 405 integrated circuit device having P-channel and N-channel MOS field effect transistors as components.
ＭＯＳ型集積回路装置の製造個数は年々増加しており、
タイプもＰチャンネルＭＯＳからＮチャンネルＭＯＳへ
、又相補型ＭＯＳへと移行しつつあり、集積度において
も年々倍の速度で高集積化されている。ＮチャンネルＭ
ＯＳ集積回路装置は集積度、高速世がすぐれており、相
補型Ｍ（）Ｓ集積回路装置は低消費電力という点ですぐ
れている。特に石油ショック以来、省資源化が望まれて
いると同時に電子機器の多くがポータブル化され小型化
されてきている為、低消費電力の相補型ＭＯＳ集積回路
装置の需要は、これから増大していくものと思われる。
しかしながら、相補型ＭＯＳ集積回路装置は、Ｎチャン
ネルＭＯＳ集積回路装置に比較して、集積度及び高速性
、特に集積度において、劣つている為、期待よりも需要
の伸びがにぶいと思われる。集積度のあがらない原因は
、大別して二つあり、一つは両チャンネルのモノリシッ
ク化という事で、両チャンネルの境界領域があつて、こ
れがデツドゾーンとなつていて、しかもその面積が比較
的大きいという点である。二つ目は一層目と二層目との
配線のコンタクト数とその大きさである。現在、相補型
ＭＯＳ集積回路装置を製造するにあたり用いる基板はＮ
型５１単結晶基板てあり、基・板内に拡散によつてＰ−
領域を形成する。The number of MOS integrated circuit devices manufactured is increasing year by year.
The type is also changing from P-channel MOS to N-channel MOS and then to complementary MOS, and the degree of integration is also increasing at a rate doubling year by year. N channel M
OS integrated circuit devices are superior in integration density and high speed, and complementary M()S integrated circuit devices are superior in low power consumption. In particular, since the oil crisis, there has been a desire to conserve resources, and at the same time, many electronic devices have become portable and downsized, so the demand for complementary MOS integrated circuit devices with low power consumption will increase in the future. It seems to be.
However, since complementary MOS integrated circuit devices are inferior to N-channel MOS integrated circuit devices in terms of degree of integration and speed, particularly in terms of degree of integration, demand for them is expected to grow more slowly than expected. There are two main reasons why the degree of integration does not increase.One is that both channels are monolithic, and there is a boundary area between both channels, which becomes a dead zone, and the area is relatively large. It is a point. The second factor is the number and size of wiring contacts between the first and second layers. Currently, the substrate used to manufacture complementary MOS integrated circuit devices is N
Type 51 single crystal substrate is used, and P- is formed by diffusion within the substrate.
Form a region.
たとえば、Ｎ（１００）３〜５Ω−ｃｍの基板に拡散深
さ６〜１５μ、表面濃度５×１０”゜Ｃｍ−゜のＰ−拡
散層を形成すると境界領域での表面濃度の変化、空乏層
の広がり、マスクずれ等を考慮すると３０〜４０μのデ
ツドゾーンが必要となる。本発明は以上のような欠点に
ついて改良したものであり、本発明の目的はＰチャンネ
ル領域とＮチャンネル領域との境界領域、いわゆるデツ
ドゾーンを小さくする事にある。For example, if a P- diffusion layer with a diffusion depth of 6-15 μm and a surface concentration of 5×10”°Cm-° is formed on a N(100) 3-5Ω-cm substrate, the surface concentration changes in the boundary region, the depletion layer A dead zone of 30 to 40 μm is required when considering the spread of the channel, mask shift, etc. The present invention is an improvement on the above-mentioned drawbacks, and an object of the present invention is to improve the boundary area between the P channel region and the N channel region. , the purpose is to make the so-called dead zone smaller.
第１図〜第５図は、本発明の実施した製造方法の一例を
、工程順を追つて断面略図を示した。FIGS. 1 to 5 are schematic cross-sectional views showing an example of the manufacturing method according to the present invention in the order of steps.
以下本発明を図によつて詳細に説明する。第１図に示す
ように、Ｎ型Ｓｉ単結晶基板１上に、所望の回路パター
ンに従つて、選択酸化膜２を周知の方法によつて作製し
、レジスト３により将来Ｐ−領域となる部分をカバーし
、このレジスト３及び選択酸化膜２とをマスクにリンイ
オンをイオン打ち込みし、Ｎ−拡散層５を形成する。Hereinafter, the present invention will be explained in detail with reference to the drawings. As shown in FIG. 1, a selective oxide film 2 is formed on an N-type Si single crystal substrate 1 according to a desired circuit pattern by a well-known method, and a resist 3 is applied to a portion that will become a P- region in the future. is covered, and phosphorous ions are implanted using the resist 3 and selective oxide film 2 as masks to form an N- diffusion layer 5.
同様に第２図に示す様にレジスト膜４を形成しＮ一拡散
領域をおおい、このレジスト膜４及び選択酸化膜２をマ
スクにボロンイオンをイオン打ち込みしＰ−拡散層６を
形成する。この後第３図に示すように、Ｎ一拡散層５と
Ｐ一拡散層６の押し込みをし、酸化膜７と窒化膜８を形
成する。さらに第４図に示すように素子領域の一部の窒
化膜８と酸化膜７をエッチング除去した後、ゲート酸化
膜９を形成し、ゲート配線１０を形成する。その上から
Ｐチャンネルの素子部にはボロンイオンをＮチャンネル
の素子部にはリンイオンをセルフアラインドーピンク几
、Ｐ＋拡散層１２、Ｎ＋拡散層１１を形成する。この上
に、第５図に示すようにＣＶＤ−ＳｌＯ２膜１５を形成
しアニールした後、拡散層に少なくとも一方向以上がセ
ルフアラインになるようにコンタクトホールをあけ、そ
の上に多結晶Ｓ１層１３を形成し、Ｐチャンネル領域に
はその上からＰ＋拡散を、Ｎチャンネル領域にはその上
からＮ＋拡散をし、その上にＮ蒸着膜１４を形成する。
その後、フォトエッチングによつて、配線を形成する。
又、必要であればこの上にパシベーシヨン膜を形成し、
ボンディングパットの穴あけをする。以上のように本発
明の製造方法を用いると、ＰチャンネルとＮチャンネル
の境界領域（デツド・ゾーン）が非常に小さくなる。Similarly, as shown in FIG. 2, a resist film 4 is formed to cover the N-diffusion region, and boron ions are implanted using the resist film 4 and selective oxide film 2 as masks to form a P-diffusion layer 6. Thereafter, as shown in FIG. 3, the N-diffusion layer 5 and the P-diffusion layer 6 are pressed together to form an oxide film 7 and a nitride film 8. Further, as shown in FIG. 4, after etching and removing part of the nitride film 8 and oxide film 7 in the element region, a gate oxide film 9 is formed and a gate wiring 10 is formed. Thereon, boron ions are formed in the P-channel element portion, phosphorus ions are applied in the N-channel element portion, and a P+ diffusion layer 12 and an N+ diffusion layer 11 are formed. After forming and annealing a CVD-SlO2 film 15 as shown in FIG. 5 on this, a contact hole is made in the diffusion layer so that at least one direction is self-aligned, and a polycrystalline S1 layer 13 is formed on it. is formed, P+ diffusion is performed from above into the P channel region, N+ diffusion is performed from above into the N channel region, and an N vapor deposition film 14 is formed thereon.
Thereafter, wiring is formed by photo-etching.
Also, if necessary, form a passivation film on this,
Drill a hole for the bonding pad. As described above, when the manufacturing method of the present invention is used, the boundary area (dead zone) between the P channel and the N channel becomes extremely small.
又、Ｐチャンネル領域、又はＮチャンネル領域内におい
ても、素子を構成する領域はすべて、Ｎ−ウェル又はＰ
−ウェルがセルフアライン的に形成されるから、基板内
の不活性部を極めて少なくすることができる。さらに本
発明では、選択酸化後に、選択酸化膜２をマスクにＰ−
ウェル及びＮ−ウェルを拡散形成するので、上訃アーウ
エル用及びＮ−ウェル用のマスクの為の酸化膜を別に設
ける必要はなく、工程が大巾に簡略できる特徴を有する
ものである。尚、本発明の応用は上記実施例における様
な、相補型ＭＯＳ−１Ｃに限るものでなく、Ｐチャンネ
ルＭＯＳ−１Ｃ及びＮチャンネルＭＯＳ−１Ｃに応用し
ても、さらには、ノンゲートセルフアライントランジス
ター構造のＩＣに応用してもその効果は全く変わらない
。又前記選択酸化膜の代りに、ウェハーを全面酸化し、
素子部を選択エッチ除去した酸化膜を使うのも可能であ
る。In addition, even within the P channel region or the N channel region, all regions constituting the device are N-well or P channel regions.
- Since the wells are formed in a self-aligned manner, the amount of inactive areas in the substrate can be minimized. Furthermore, in the present invention, after selective oxidation, P-
Since the well and N-well are formed by diffusion, there is no need to separately provide oxide films for masks for the upper well and the N-well, and the process can be greatly simplified. Note that the application of the present invention is not limited to complementary MOS-1C as in the above embodiments, but can also be applied to P-channel MOS-1C and N-channel MOS-1C, and furthermore, to non-gate self-aligned transistors. Even when applied to structural ICs, the effect remains the same. Also, instead of the selective oxidation film, the entire wafer is oxidized,
It is also possible to use an oxide film whose element portion is selectively etched away.
第１図から第５図は本発明の一例の製造工程順を追つた
断面図である。
１・・・・・・Ｎ型Ｓｉ型単結晶基板、２・・・・・フ
ィールド酸化膜、３，４・・・・・ルジスト膜、５・・
・・・・Ｎ一拡散層、６・・・・・・Ｐ一拡散層、７・
・・・・酸化膜、８・・・・・・窒化膜、９・・・・・
・ゲート酸化膜、１０・・・・・・ゲート酸化膜、１１
・・・・・・Ｎ＋拡散層、１２・・・・・Ｐ＋拡散層、
１３・・・・・ポリシリコン層、１４・・・・・・ＡＩ
蒸着膜、１５・・・・・・ＣＶＤ−ＳｉＯ２膜。FIGS. 1 to 5 are cross-sectional views showing the order of manufacturing steps of an example of the present invention. 1... N-type Si type single crystal substrate, 2... Field oxide film, 3, 4... Lujist film, 5...
...N-diffusion layer, 6...P-diffusion layer, 7.
...Oxide film, 8...Nitride film, 9...
・Gate oxide film, 10... Gate oxide film, 11
......N+diffusion layer, 12...P+diffusion layer,
13...Polysilicon layer, 14...AI
Vapor deposited film, 15...CVD-SiO2 film.
Claims (1)
て成形したＮチャンネル領域及びＰチャンネル領域と、
選択酸化法により形成したフィールド酸化膜領域とを有
する、相補型ＭＯＳ集積回路装置において、前記Ｎチャ
ンネル領域及びＰチャンネル領域は、前記フィールド酸
化膜をマスクとして、前記ボロン及び前記リンを打ち込
むことにより形成する事を特徴とする相補型ＭＯＳ集積
回路装置の製造方法。1. An N-channel region and a P-channel region formed on a P-type or N-type substrate by implanting boron and phosphorus;
In a complementary MOS integrated circuit device having a field oxide film region formed by a selective oxidation method, the N channel region and the P channel region are formed by implanting the boron and the phosphorus using the field oxide film as a mask. 1. A method for manufacturing a complementary MOS integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53015196A JPS6041870B2 (en) | 1978-02-13 | 1978-02-13 | Method for manufacturing complementary MOS integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53015196A JPS6041870B2 (en) | 1978-02-13 | 1978-02-13 | Method for manufacturing complementary MOS integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54122982A JPS54122982A (en) | 1979-09-22 |
| JPS6041870B2 true JPS6041870B2 (en) | 1985-09-19 |
Family
ID=11882098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53015196A Expired JPS6041870B2 (en) | 1978-02-13 | 1978-02-13 | Method for manufacturing complementary MOS integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041870B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636425B2 (en) * | 1983-02-23 | 1994-05-11 | テキサス インスツルメンツ インコ−ポレイテツド | Method for manufacturing CMOS device |
| US5091332A (en) * | 1990-11-19 | 1992-02-25 | Intel Corporation | Semiconductor field oxidation process |
-
1978
- 1978-02-13 JP JP53015196A patent/JPS6041870B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54122982A (en) | 1979-09-22 |
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