JPS6042630B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6042630B2 JPS6042630B2 JP51152426A JP15242676A JPS6042630B2 JP S6042630 B2 JPS6042630 B2 JP S6042630B2 JP 51152426 A JP51152426 A JP 51152426A JP 15242676 A JP15242676 A JP 15242676A JP S6042630 B2 JPS6042630 B2 JP S6042630B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- voltage
- polycrystalline silicon
- thin film
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にゲート入力電圧の許容範囲を
拡大せしめた相補形絶縁ゲート電界効果トランジスタ（
以下ＣＭＯＳという）の入力保護装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a complementary insulated gate field effect transistor (
The present invention relates to an input protection device for CMOS (hereinafter referred to as CMOS).
従来、ＣＭＯＳの入力保護装置が第１図の点線内に示し
た様に、抵抗Ｒ、及び二つのダイオードＤ、、Ｄ２から
構成されていることは公知である。It is conventionally known that a CMOS input protection device is composed of a resistor R and two diodes D, D2, as shown within the dotted line in FIG.
第２図はこの入力保護装置をＮ形半導体基板１に形成し
た場合の断面図を示し、Ｐ利用拡散層２により抵抗Ｒ、
を、Ｐ利用拡散層２とＮ形基板１によりダイオードＤ、
を、更にＮ利用拡散層とＮ形基板１によりダイオードＤ
２をそれぞれ形成し、Ｎ形基板１は電源＋ ＶＤに接続
され、Ｐ−ウェル３は接地されている。また６は金属配
線を示し、図示はしていないがＮ形基板１にはＰチャン
ネルトランジスタが、Ｐ−ウェル３にはＮチャンネルト
ランジスタが形成されている。このような構成による入
力保護装置は、入力端子７に印加される正の過大人力電
圧をダイオードＤ、により、負の過大人力電圧をダイオ
ードＤ２によりそれぞれクランプしてトランジスタのゲ
ート電極を保護するものであるが、極めて過大な正電圧
が印加された場合には、その電流が抵抗Ｒ、により抑制
されすに直接ダイオードＤ、を通つてＮ形基板１に流れ
込むこととなるため、寄生サイリスタ効果を引き起こし
たり、配線損傷を生せしめたりすることが少くなかつた
。また、ゲート入力電圧の許容範囲は、正の電圧が電源
＋ ＶＤとダイオードＤ、の飽和電圧との和に、負の電
圧がダイオードＤ。を飽和させ得る電圧に限定されるた
め、例えゲート電極を破壊する程までには大きくない電
圧でもダイオードＤ、又はＤ２によりクランプされてし
まうため、入力電圧マージンは大きくとり得なかつた。
本発明の目的は上記の欠点を除去してゲート入３力電圧
の許容範囲を拡大せしめた入力保護装置を提供すること
てある。FIG. 2 shows a cross-sectional view of this input protection device formed on an N-type semiconductor substrate 1, in which a resistance R,
, the diode D is formed by the P diffusion layer 2 and the N type substrate 1,
Furthermore, a diode D is formed by an N-based diffusion layer and an N-type substrate 1.
2, the N-type substrate 1 is connected to the power supply +VD, and the P-well 3 is grounded. Further, numeral 6 indicates metal wiring, and although not shown, a P-channel transistor is formed in the N-type substrate 1 and an N-channel transistor is formed in the P-well 3. The input protection device with such a configuration protects the gate electrode of the transistor by clamping the positive excessive human power voltage applied to the input terminal 7 with the diode D, and clamping the negative excessive human power voltage with the diode D2. However, if an extremely excessive positive voltage is applied, the current will be suppressed by the resistor R and directly flow into the N-type substrate 1 through the diode D, causing a parasitic thyristor effect. There were many cases where this caused damage to the wiring. Also, the allowable range of gate input voltage is that a positive voltage is the sum of the power supply +VD and the saturation voltage of diode D, and a negative voltage is the sum of the saturation voltage of diode D. Since the voltage is limited to a voltage that can saturate the gate electrode, even if the voltage is not large enough to destroy the gate electrode, it will be clamped by the diode D or D2, so the input voltage margin cannot be large.
SUMMARY OF THE INVENTION An object of the present invention is to provide an input protection device which eliminates the above-mentioned drawbacks and expands the allowable range of gate input voltage.
次に本発明を図面を参照して説明する。Next, the present invention will be explained with reference to the drawings.
第３図は本発明の一実施例を示す図で、従来の入力保護
装置にタイオートＤ。FIG. 3 is a diagram showing an embodiment of the present invention, in which tie auto D is used as a conventional input protection device.
及びＤ、を逆方向にｉ接続し、それらの逆耐圧を利用し
て入力電圧の許容範囲を拡大するものであるが、タイオ
ートＤ。及ひＤ、は基板中に不純物拡散層を利用して形
成するとその降状電圧が−１５Ｖ以上に大きくなつて過
大人力電圧がクランプされる前にゲート電極が破壊され
てしまうことと、逆方向に接続する二つのダイオードを
基板中に作ることが比較的困難であることから、基板表
面上に多結晶シリコン薄膜で降状電圧が低くなるよう形
成する。第４図は多結晶シリコン薄膜に形成したＰ−Ｎ
接合の電圧一電流特性を示す図で、飽和電圧は０．５Ｖ
、降状電圧は−４Ｖ程度である。and D are connected in reverse directions, and the allowable range of input voltage is expanded by utilizing their reverse withstand voltage. And D, if an impurity diffusion layer is formed in the substrate, the falling voltage will increase to more than -15V and the gate electrode will be destroyed before the excessive human voltage is clamped. Since it is relatively difficult to fabricate two diodes connected to the substrate in the substrate, a polycrystalline silicon thin film is formed on the substrate surface so that the voltage drop is low. Figure 4 shows P-N formed on a polycrystalline silicon thin film.
This is a diagram showing the voltage-current characteristics of a junction, and the saturation voltage is 0.5V.
, the falling voltage is about -4V.
従つてゲート入力電圧の許容範囲は正及び負方向共に４
Ｖづつ拡大されることとなる。拡大される範囲はこのよ
うにダイオードＤ３及びＤ４の降状電圧により決定され
ることとなるが、その幅は多結晶シリコンに拡散される
不純物濃度により異なる値をとることは勿論てあり、一
例として示した第４図の特性をもつＰ−Ｎ接合は、Ｐ形
不純物を１０１９ｃｍ−３、Ｎ形不純物を１『〜１σ１
ｃ７ｘ−３にしたものである。第５図は第４図に示した
入力保護装置をＮ形半導体基板１１内に形成した断面図
を示し、Ｐ＋形多結晶シリコン薄膜１７は抵抗Ｒを、Ｎ
＋形多結晶シリコン薄膜１８及びＰ＋形多結晶シリコン
薄膜１９がダイオードＤ３を、またＮ＋形多結晶シリコ
ン薄膜１８及びＰ＋形多結晶シリコン薄膜１９″がダイ
オードＤ３を、またＰ＋形多結晶シリコン薄膜１７及び
Ｎ＋形多結晶シリコン薄膜１『がダイオードＤ４をそれ
ぞれ形成すると共に、従来と同じくＰ＋形拡散層１２と
Ｎ形基板１１とによりダイオードＤ１を、Ｎ＋形拡散相
１４とＰ−ウェル１３とによりダイオードＤ３形成して
いる。またＰ＋形拡散層１５は金属配線２１とのコンタ
クト部であり、２０は酸化膜を、他の２１も前と同様金
属配線をそれぞれ示す。また第６図は第５図に示した基
板の平面図でそれぞれの連続番号は第５図に示したもの
と対応している。本発明によれは基板表面の絶縁膜上に
形成した多結晶シリコン薄膜によるダイオードを逆方向
に接続することによりゲート入力電圧の許容範囲を拡大
できるばかりでなく、抵抗をも多結晶シリコン薄膜で形
成しているため、基板に流れ込む電流は抵抗を通過せざ
るを得ず、従つて過大人力電圧が入力端子に印加された
場合においてもその電流は極めて抑制されたものとなり
、従来問題になつていた寄生サイリスタ効果などを防止
することも可能となる。Therefore, the allowable range of gate input voltage is 4 in both positive and negative directions.
It will be expanded by V. The expanded range is thus determined by the falling voltage of the diodes D3 and D4, but the width will of course take a different value depending on the impurity concentration diffused into the polycrystalline silicon. A P-N junction with the characteristics shown in Fig. 4 has a P-type impurity of 1019cm-3 and an N-type impurity of 1'~1σ1.
It was changed to c7x-3. FIG. 5 shows a cross-sectional view of the input protection device shown in FIG.
+ type polycrystalline silicon thin film 18 and P+ type polycrystalline silicon thin film 19 form diode D3, N+ type polycrystalline silicon thin film 18 and P+ type polycrystalline silicon thin film 19'' form diode D3, and P+ type polycrystalline silicon thin film 17 and N+ type polycrystalline silicon thin film 1'' respectively form a diode D4, and as in the conventional case, a diode D1 is formed by the P+ type diffusion layer 12 and the N type substrate 11, and a diode is formed by the N+ type diffusion layer 14 and the P- well 13. The P+ type diffusion layer 15 is a contact portion with a metal wiring 21, 20 is an oxide film, and the other 21 is a metal wiring as before.Furthermore, FIG. In the plan view of the substrate shown in FIG. 5, each serial number corresponds to that shown in FIG. Not only can the permissible range of gate input voltage be expanded by connecting, but also because the resistor is formed of a polycrystalline silicon thin film, the current flowing into the substrate has no choice but to pass through the resistor, thus preventing excessive manual voltage. Even when the current is applied to the input terminal, the current is extremely suppressed, and it is also possible to prevent the parasitic thyristor effect, which has been a problem in the past.
このように本発明は、入力電圧の許容範囲拡大及び寄生
サイリスタ効果の防止等に極めて有用なものであり、特
にシリコンゲートＣＭＯＳに適用する場合には従来の製
造工程を増加する必要が全くないため、その効果は益々
顕著となる。As described above, the present invention is extremely useful for expanding the allowable range of input voltage and preventing parasitic thyristor effects, and particularly when applied to silicon gate CMOS, there is no need to increase the conventional manufacturing process. , the effect becomes more and more noticeable.
第１図及ひ第２図は従来の入力保護装置と基板に形成し
た断面図、第３図及び第５図は本発明の一実施例を示す
入力保護装置と基板に形成した断面図、第６図は第５図
に示したものの平面図、第４図は多結晶シリコン薄膜に
よるダイオードの電圧一電流特性図てある。
１，１１・・・・・Ｎ形半導体基板、２，１２，１５・
・Ｐ＋形拡散層、３，１３・・・・・・Ｐ−ウェル、４
，１４・・・・・・Ｎ＋形拡散層、５，１６，２０・・
・・・・酸化膜、６，２１・・・・・金属配線、７・・
・・・・入力端子、１７，１８，１８″，１９・・・・
・・多結晶シリコン薄膜、Ｒ・・・・・・抵抗、Ｄｌ，
Ｄ２，Ｄ３，Ｄ４・・・・・・ダイオード。1 and 2 are cross-sectional views of a conventional input protection device formed on a board, and FIGS. 3 and 5 are cross-sectional views of an input protection device and a board formed on an embodiment of the present invention. FIG. 6 is a plan view of the device shown in FIG. 5, and FIG. 4 is a voltage-current characteristic diagram of a diode made of a polycrystalline silicon thin film. 1, 11...N-type semiconductor substrate, 2, 12, 15...
・P+ type diffusion layer, 3, 13...P- well, 4
, 14...N+ type diffusion layer, 5, 16, 20...
...Oxide film, 6,21...Metal wiring, 7...
...Input terminal, 17, 18, 18'', 19...
...Polycrystalline silicon thin film, R...Resistance, Dl,
D2, D3, D4...Diode.
Claims (1)
回路が、ゲート電極と前記トランジスタの電源端子間に
接続され、ゲート電極に印加される過大入力電圧に対し
て順方向にバイアスされて飽和するダイオードと、逆方
向にバイアスされて降伏する多結晶シリコン薄膜からな
るダイオードとが直列接続されたダイオード対、及び前
記ダイオードに流れる電流を抑制せしめる多結晶シリコ
ン薄膜抵抗とを備えていることを特徴とする半導体装置
。1. An input protection circuit for a complementary insulated gate field effect transistor includes a diode connected between a gate electrode and a power supply terminal of the transistor, and which is forward biased and saturated with respect to an excessive input voltage applied to the gate electrode; A semiconductor device comprising: a pair of diodes connected in series with a diode made of a polycrystalline silicon thin film that is biased in a reverse direction and breaks down; and a polycrystalline silicon thin film resistor that suppresses the current flowing through the diode. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51152426A JPS6042630B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51152426A JPS6042630B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5376677A JPS5376677A (en) | 1978-07-07 |
| JPS6042630B2 true JPS6042630B2 (en) | 1985-09-24 |
Family
ID=15540247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51152426A Expired JPS6042630B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042630B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591173A (en) * | 1978-12-28 | 1980-07-10 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS5591172A (en) * | 1978-12-28 | 1980-07-10 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS55166951A (en) * | 1979-06-14 | 1980-12-26 | Mitsubishi Electric Corp | Surge preventive circuit for bipolar integrated circuit |
| JPS57141962A (en) * | 1981-02-27 | 1982-09-02 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61185962A (en) * | 1985-02-13 | 1986-08-19 | Nec Corp | Complementary mos integrated circuit |
| JPH0770707B2 (en) * | 1985-07-31 | 1995-07-31 | 日本電気株式会社 | CMOS input protection circuit |
| JPH0766965B2 (en) * | 1987-02-27 | 1995-07-19 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP5603277B2 (en) * | 2011-03-29 | 2014-10-08 | セイコーインスツル株式会社 | ESD protection circuit for semiconductor integrated circuit |
-
1976
- 1976-12-17 JP JP51152426A patent/JPS6042630B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5376677A (en) | 1978-07-07 |
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