JPS6043539B2 - Memory-switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory switching circuit that can switch the memory connected to a CPU after a certain period of time after power is turned on.

Among CPUs recently used in various industrial fields, Intel's 8080 and 8085, for example, start execution from memory address 0 when the power is turned on.

Therefore, at least several bytes starting from address o of the memory must be a ROM that retains its stored contents even when the power is turned off. However, the storage capacity of ROM per chip is
Small ones are about the size of a 2-bit bite, and large ones are about the size of a warehouse bite, so even if you use a water bite ROM,
The address space from address $000 to $07FF in binary notation is exclusively occupied by the startup ROM (so-called boot ROM), and the memory contents can be changed freely.
The ROM that stored programs other than the AM and start-up programs had to be placed at subsequent addresses.
However, since the startup ROM as described above is used only once when the power is turned on, there is a problem in that it is extremely inconvenient to have such a rarely used memory occupy a large address space. The present invention has been made to solve these problems of the conventional example, and after a certain period of time has passed after the power is turned on, the R for starting is turned off.
Another object of the present invention is to provide a memory switching circuit that can automatically disconnect the OM from the CPU and switch to another RAM or ROM. The configuration of the present invention will be described below with reference to illustrated embodiments.

FIG. 1 shows a circuit diagram of an embodiment of the present invention,
In the figure, 1 is a starting ROM (so-called boot RO).
M), and 2 is a RAM in which data can be freely read and written. These ROMI and RAM2 have an 8-bit data output terminal and an 11-bit address terminal, and the 8-bit data output terminal is connected to the eight data buses D of the CPU. --Connected to D7, and the 11-bit address terminal is connected to 16 of the CPU.
Of the address buses A0-A, 5 of *, it is connected to tiles ~A, o. By the way, these data buses D0 to D
7 and address A. --If two or more memories such as ROM1 and RAM2 are connected to A15 at the same time, data will be confused, so ROMI and RAM2 are each provided with a chip select terminal CS, and this chip select terminal is set to L level. The memory is designed to operate only when In addition, RAM2 has a write signal terminal W↑ that becomes L level when writing data.
is provided. Reference numeral 3 designates a timer circuit that operates when the power is turned on, and when the power supply voltage Vcc reaches H level, the capacitor C is charged via the resistor R1, and its terminal voltage increases.

As a result, after a while after the power is turned on, the output of the Schmitt buffer 4 becomes L level, the NAND date 5 is opened, the RAM 2 is chip-selected, and the inverter 6
The NAND gate 7 is closed via the ROM1 to prevent the chip select signal from being sent to the ROM1. On the other hand, immediately after the power is turned on, the output of Schmitt buffer 4 is H.
Since the NAND gate 5 is at the high level, the NAND gate 5 is closed and RAM2 is not chip-selected, and the inverter 6
Since the NAND gate 7 is opened via the ROM1, the ROM1 is chip-selected. Therefore, immediately after the power is turned on, the starting ROM1 is selected, and when the timer circuit 3 is activated some time after the power is turned on, the RAM2 is selected and the starting ROM1 is disconnected. Note that R2 is a resistor for increasing the charge discharging speed of the capacitor C when the power is turned off. Next, Figure 2 is a memory map showing the above-mentioned memory switching operation. When the power is turned on, the CPU reads data from memory address 0 and starts execution.
If OMl is placed at an address starting from address O in the memory, the startup operation will be performed automatically, and ROMl will block transfer the necessary part of its own memory to other RAM2a as appropriate, and The CPU jumps to a specific address and operates the CPU according to the contents of the RAM 2a. This block transfer of data is performed. If you don't want to, always use CP in addition to the starting ROM1.
Another ROM connected to U may be provided in place of RAM2a. However, timer circuit 3
If the delay time is set longer than the time required to complete the above operations, the output of timer circuit 3 will cause R
OM1 is switched to RAM2 so that the memory address space can be used effectively. In addition, instead of RAM2, ROM for starting
By switching and connecting another ROM storing a program or data different from ROM 1, it is possible to arrange ROMs with different functions within the address space of the starting ROM 1. Furthermore, when carrying out the present invention, the entire circuit as described above is integrated into one I/O circuit.
It does not matter if it is incorporated into C. The present invention is configured as described above, and includes a starting ROM in which a starting program is written, and a starting ROM.
M and other memories located in the same address space,
Since the chip is selected by the output of a timer circuit whose output is inverted after a predetermined time has elapsed after the power is turned on, this ROM for starting is C
This prevents the startup ROM, which is used only once for startup, from monopolizing a large address space in memory, since it is disconnected from the PU and other memories such as RAM and ROM are connected in its place. This has the advantage that limited address space can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a memory map for explaining the operation of the same. 1 is a ROM12, CPU13 is a timer circuit, and 5 and 7 are NAND gates.

Claims (1)

[Claims] 1 A starting ROM connected to the CPU that reads instructions from a specific address in the memory and starts execution when the power is turned on, and a starting ROM in which a starting program is written from the above specific address, and a starting ROM with the same address as this starting ROM. Other memories placed in the space, a timer circuit whose output is reversed after a predetermined time has passed after the power is turned on, and a ROM that operates based on the output of the timer circuit and is used for starting when the power is turned on.
A memory switching circuit comprising a switching circuit that sends a chip select signal to the other memory and sends a chip select signal to the other memory when the output of the timer circuit is inverted.