JPS6043587B2 - MIS input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to ECL (Emitter Coupled L
The present invention relates to an input circuit composed of MISFETs (insulated gate field effect transistors) that use signals in different level ranges, such as output signals (or Logic), as input signals.

In electronic computer systems, ECL circuits and MIS
It is composed of a mixture of circuits.

For example, a case may be considered in which an information processing device is configured with an ECL circuit and an MIS memory is used as a storage device.
In this case, since the level range of the ECL signal has an amplitude of about 600 mV, it cannot be input directly to the MIS logic circuit, and a level conversion circuit has been used.

That is, it has been difficult to form a reference voltage for identifying the small amplitude signal using a MISFET circuit due to large variations in elements. This invention is based on the former Cl.
This was done to provide a 415 input circuit that can directly input signal levels.

This invention uses an MIS differential amplifier circuit as an MIS input circuit, and uses a voltage difference between ECL level signals having opposite phases to each other as a reference voltage signal, which is approximately halved by a voltage dividing means such as a voltage dividing resistor. This is what I intend to use.
Hereinafter, the present invention will be specifically explained with reference to Examples. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This circuit shows an example in which the MIS memory circuit is directly accessed by the ECL control circuit. Since the MIS memory circuit of this embodiment is activated by chip selection signals CE and CV which are in opposite phases to each other, these are used to form the reference voltage of the MIS input circuit.

That is, the ECL circuit that forms the chip selection signals CE and CE includes differential transistors Ql and Q that share the emitter.
2 and this common emitter is provided with a constant voltage at the base.
A constant current circuit composed of a transistor Q3 to which B is applied and an emitter resistor R3, load resistors Rl and R2 respectively provided on the collector, and the differential transistor Ql,
It is composed of emitter follower output transistors Q4 and Q5 with the collector output of Q2 applied to the base, and the ECL reference voltage (Vre) is applied to the base of the transistor Q2.
f) and a chip selection signal CE″ is applied to the base of the transistor Q1 to select the output transistors Q4 and Q.
5, the chip selection signal CE is sent to the MIS memory side.
, to obtain CV. On the MIS memory circuit side, voltage dividing resistors R4 and R5 set to the same value are provided between the chip selection signal terminals, and a noise absorbing capacitor C is provided between the voltage dividing output and the AC ground terminal. Voltage (Vre
f'').

Then, the differential MISFETs QlO and Qll with a common source and the drain load MISF
ETQl2,Qe.

and a source resistor R6 constitute a MIS differential amplifier circuit, and the reference voltage (Vref'') is applied to the gate of MISFET Qll of this differential circuit, and the other MISFE
The output signal X generated by the ECL circuit 1 similar to the above is directly connected to the gate of TQlO. input to obtain the level identified signal X, or x. Note that the chip selection signal CE,
Identification of d100 and identification of other information are also performed using the reference voltage (Vr
This is carried out by a MIS differential amplifier circuit similar to the above, which commonly uses ef'').

In this embodiment circuit, as shown in FIG. 2, the ECL level signals CE, CP! are in opposite phases to each other. ．． Since the reference voltage (Vref'') is formed by resistor division using , the intermediate voltage follows the dispersion and fluctuation of the signal level on the ECL circuit side, and highly accurate signal identification can be realized.

Further, the intermediate voltage is determined by the resistance ratio, and since the resistance ratio formed in the monolithic semiconductor integrated circuit can be designed with high precision, it is easy to obtain an intermediate voltage of approximately 1/2.

As a result, the ECL logic circuit and the S logic circuit can be directly connected, and it is expected that the system in the digital control circuit including these will be simplified, faster, and lower in power consumption. The present invention is not limited to the embodiment described above, and the capacitor C for noise absorption when the ECL signals CE and CE change can be omitted by using the gate capacitance in the MIS differential amplifier circuit. Furthermore, in order to reduce the number of input terminals on the MIS logic circuit side, the ECL signal that forms the reference voltage signal (■Ref'') may be an input signal of the MIS logic circuit, such as the chip selection signal CE, etc. described above. is preferable, but the reference voltage (V
It is also possible to use a special pulse signal or the like that forms only ref'').

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of a reference voltage generating circuit. 1...ECL logic circuit.

Claims (1)

[Claims] 1. A first differential MI having a pair of input terminals and a gate thereof connected to one input terminal of the pair of input terminals.
SFET, and a first second differential MISFET whose gate is connected to the other input terminal of the pair of input terminals.
a differential amplifier circuit, which has an ECL level signal outputted from the first ECL circuit and is supplied to the first differential MISFET via the pair of input terminals; and a second ECL circuit.
first and second terminals formed by an L circuit and to which mutually opposite phase ECL level signals are applied;
voltage dividing means connected between the terminals and generating a divided voltage output of a potential approximately intermediate between the potentials of the first terminal and the second terminal, and the divided voltage output of the voltage dividing means is connected to the differential amplifier. A MIS input circuit, characterized in that the signal is supplied to the second differential MISFET via the other input terminal of the circuit. 2. The voltage dividing means is provided between a pair of voltage dividing resistors having substantially the same resistance value and connected in series between the first and second terminals, and a common connection point of the voltage dividing resistors and a power supply terminal. 2. The MIS input circuit according to claim 1, comprising: