JPS6044677B2 - Audio output method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio output method for eliminating click sounds generated when outputting synthesized sounds in integrated circuits for speech synthesis, etc. This invention relates to an audio output method that removes click sounds by adding a gentle waveform.

Generally, when turning on the power to an audio amplifier circuit, if the input signal is not at ground level, a clicking sound will be generated at the same time as the power is turned on.

For this reason, conventionally, the input signal level of the audio amplifier circuit has been set to the ground level before the power is turned on, but even with this method, the rise of the audio output
If the output level suddenly changes during the fall, a clicking sound will still occur.

In order to eliminate the occurrence of the above-mentioned lick sounds, circuits are designed to minimize level changes, and speakers that do not generate the above-mentioned noise due to their frequency characteristics are used. However, there were problems such as the circuit configuration becoming complicated and the sound quality of the sound output from the speakers deteriorating.

The present invention has been made to solve the above-mentioned problems in the conventional audio output method, and eliminates the click sound output from the speaker when the power is turned on by making the change in the audio output signal waveform gentle before and after. The purpose of the present invention is to provide an audio output method that allows the following.

Therefore, when outputting an audio signal from an integrated circuit for speech synthesis, the present invention adds a waveform having a predetermined gradient from a logic level to a center level before and after the audio signal output waveform output from the integrated circuit. , is characterized in that a waveform having a predetermined slope from the center level to the logic level is added.

Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 shows an electronic desktop calculator (hereinafter abbreviated as a calculator) having an integrated circuit for speech synthesis to which the present invention is applied.

) is shown. In FIG. 1, 11 is a one-chip large-scale integrated circuit (hereinafter abbreviated as LSI).

), and this controller 11 is equipped with various external connection terminals. 12 is an address bus, 13 is a data bus, and 14 is a chip enable signal line. External to the controller 11 is a read-only memory 15 (hereinafter abbreviated as external ROM15).

) are connected. Reference numeral 16 denotes an audio signal output line, which is connected to an audio amplification device 17.

A speaker 18 is connected to the output line of this audio amplification device 17. Further, 19 is one terminal of a port for outputting a signal for power control of the audio amplifying device 17 to the audio amplifying device 17. 20 is a Stroop signal output line, 21
is a key return signal line, and these strobe signal line 20 and key return signal line 21 are connected to a key input device 22.

23 is a common signal line, and 24 is a segment signal line, which are connected to a liquid crystal display device 25.

A main program for operating as a calculator and audio data are stored in advance in Somozawa 0M15.

As will be described later, the controller 11 includes a read-only memory, a read-write memory, an arithmetic control circuit, etc., and a speech synthesis control program is stored in advance in the read-on memory. Because of this configuration,
The controller 11 has versatility as a controller for speech synthesis equipment.

In other words, even if the equipment is different, the synthesized speech words to be output are different, and the specifications are different, Tozawa 0M15
By simply changing the contents of , changing the key top display, and changing the segment configuration of the liquid crystal display 25,
1 itself can be used without any modification. FIG. 2 shows the system configuration of the controller 11.

In FIG. 2, numeral 31 is a read-only memory (hereinafter abbreviated as internal ROM 3l) that stores in advance an algorithm (processing program) for voice synthesis control, and has a capacity of 16 bits and 512 steps. A1~Al
4 is an address signal terminal for outputting an address signal to the external ROM 15, and D1 to D8 are data signal terminals for reading data from the ROM 15.

32 is a program counter, and 33 is a data pointer. The program counter 32 is a counter that indicates the address for voice synthesis control in the built-in ROM 3l and the address of the main program in the external ROM 15.

On the other hand, the data pointer 33 is a pointer that indicates the position (address) of the audio data recorded in the external ROM 15. 34 is read/write memory (hereinafter referred to as R
It is written as AM34.

), and the RAM 34 contains 8 bits x 64 = 512
There is an area used for voice synthesis control having a capacity of bits, an area used for calculator calculations, and an area for display. Each bit in the display area corresponds to each segment of the liquid crystal display device 25, and by writing a display pattern in this area, the pattern is displayed. 35 is an address register of the RAM 34.

A certain area of the RAM 34 may be used as a stack for a subroutine, and 36 is a stack pointer indicating its position. 37 is an internal data bus signal, a signal output from the built-in 0M31, and an accumulator 38.
This is an arithmetic circuit that performs arithmetic and logical operations on signals output from the circuit.

Further, 39 is a flip-flop for discrimination, 40 is a carry (half-carry) flip-flop from the 4th bit,
41 is a carry flip-flop. 42 is an instruction decoder which decodes the upper 8-bit operation code output from the built-in OM31 and outputs a micro order.

Reference numeral 43 denotes a power control section, which controls oscillation/stopping of the clock generator 44, generation/stopping of the system clock, ON/OFF switching of the display power source, and the like.

That is, during calculation, system clocks φ1 and φ2 are output, and the entire system operates. Also, in the displaying state, only the display control section is operated by stopping the generation of system lock. The controller 11 shown in FIG.
Since it is configured with an OS, power consumption can be kept low by stopping the system lock. VGG is a negative power terminal of this controller 11.

CGl and CG2 are terminals to which a resistor or ceramic filter for oscillating the clock generator 44 is connected. Incidentally, this oscillation frequency is 131 KHz. 45 is an oscillator for a clock function, and this oscillation waveform is divided by a frequency divider 46.

Xl and X2 are terminals to which a crystal oscillator is connected. The input of the frequency divider 46 is constituted by a program logic array (PLA), which divides the output of any one of the four oscillators 45 from the clock generator. The final stage of the frequency divider 46 outputs a one second signal 1S. 47
is a common signal generation circuit of the liquid crystal display device 25, and H1
~H4 is a common signal output terminal.

The common signal generating circuit 47 also outputs an address signal for the display area of the RAM 34.

48 is a buffer that generates segment signals to the liquid crystal display device.

S1 to S25 are terminals connected to segment terminals of the liquid crystal display device 25. Ki is a 6-bit input port, a key input device 22 is connected to K1 to K6, and a key return signal is input. Ti is an 8-bit output port, a key input device 22 is connected to T1 to T8, and a key strobe signal is output. Fi is a 4-bit output port, and in this embodiment, it is connected to external RO from F4.
The signal of the most significant bit of the M15 head address signal is output. PVi is a latch circuit that latches 8-bit audio data output from the arithmetic circuit 37. 50 is a D/A converter, and DAi is a terminal for outputting an analog audio signal.

51 is an impedance conversion circuit, which connects DAj and DAO.
By connecting a return resistor (not shown) between them, the speaker can be driven by simply connecting a simple external amplifier circuit.

CEO is a terminal that outputs a chip enable signal to external ROM15.

Although not shown, the chip enable signal generation circuit operates on a micro-order basis. The operation will be explained below.

FIG. 3 shows the relationship between the addresses of the built-in ROM 3l and the external ROM 15.

Built-in ROM 3l is 16 bits long and has address 000.
Close the area from 0-01FF. Sotomasawa 0M15 is 8
It has a bit length and can use the area from addresses 0000 to 7FFF. VP is a voice synthesis control program, and VP is a main program to function as a calculator.
VDl and VD2 indicate storage areas for audio data, respectively.

The aforementioned program counter 32 specifies the address of the program area of this speech synthesis control program VP and main program MP, while the data pointer 33 specifies the address of the program area of the voice synthesis control program VP and main program MP.
Specify the address of the entire area of Sawa 0M15. That is, when reading data from the external storage λ0M15, the address information of the data to be read is set in the data pointer 33, and the contents of the external ROM15 are read. Furthermore, when executing the instructions of the voice synthesis control program VP or the main program MP, the value of the program counter 32 is counted up each time the instruction of the step specified by the program counter 32 is executed. Execute sequentially.
The speech synthesis control program VP has a long 16-bit step, so even if the system clock is relatively slow,
It is possible to perform speech synthesis that requires high-speed calculation.

The upper 8 bits are an operation code and are output to the instruction decoder 42 as shown in FIG. 2, and the lower 8 bits are an operand and are output to the internal data bus. On the other hand, the instruction read from the external ROM 15 is input internally from the external data bus and input to the instruction decoder 42.

Data is also input to the internal data bus. moreover,
A RAM (not shown) can also be connected externally.
Like the external ROM15, the address bus and data bus are common, and the chip enable signal and read/write signal are
It can be used by outputting it to the RAM from the port. The processing procedure of the entire apparatus is shown in FIG.

In other words, by executing the main program MP within v<0M15, processes such as key identification, calculation, and display of calculation results are performed, and when audio notification is performed, the word code corresponding to a predetermined word is input to the accumulator. 38 and jumps to the voice synthesis control program VP (subroutine call), the word is voiced. FIG. 5 shows the power supply of the audio amplification device 17 and the waveform of the audio output signal.At the time T1, power is supplied to the audio amplification device 17, and the audio signal output waveform is in the section a, In other words, a ramp waveform is output from the "L" level to the center level. The time between T1 and T2 is 5 to 10n.
The time is about 1 sec. Subsequently, audio waveform b is output. After the output of b is completed, a ramp waveform is output from the center level to the ゛゜L゛ level. Then, at time T4, the amplifier power supply is turned off. On the other hand, FIG. 6 shows a conventional audio signal output waveform.

In other words, a sharp level change occurs from the ゜゜L゛ level to the center level at the beginning of the audio signal output waveform, resulting in a click sound. The same applies when the audio signal output waveform ends. FIG. 7 is a flowchart of this series of processing. First, in step 101, all 0s are input to the latch circuit PVi mentioned above, and the output of the D/A converter 50 is set to the °L level, and then, in step 102, F1 of the F port is set.

The power of the audio amplifying device 17 is turned on by the signal F1. After that, in steps 103, 104, 105,
After sequentially outputting a rising waveform, an audio waveform, and a falling waveform, in step 106, the above F1 is reset and the power to the audio amplification device 17 is turned off. There are basically two ways to output the rising waveform and falling waveform.

By one operation, the value given to the latch circuit PVi is incremented or decremented.

The two-ramp waveform is recorded in advance as one audio waveform.

Method 1 synthesizes a ramp waveform by sequentially performing addition or subtraction operations from the "L" level or "W5 level" to the center level over time, and by creating the command in advance. can be done.

Method 2 treats the rising waveform and the falling waveform as one word, and can be implemented even in a system that does not have commands as shown in 1. As is clear from the detailed explanation above, the present invention adds a waveform with a gentle slope before and after the audio signal output waveform output from the integrated circuit for audio synthesis, and adds a waveform with a gentle slope before and after the audio signal output waveform to the speaker Since the fluctuation of the input signal is made gentler, it is possible to eliminate the occurrence of a clicking sound when the power is turned on using a normal circuit configuration.

Note that the present invention is also effective in a method of outputting a synthesized sound as PWM output.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an electronic desktop calculator having an integrated circuit for speech synthesis to which the present invention is applied, Fig. 2 is a block diagram showing the system configuration of the controller, and Fig. 3 is a block diagram of the ROM built into the controller and ? An explanatory diagram for explaining the relationship between 0M addresses, FIG. 4 is a flowchart of the processing procedure performed in the electronic desk calculator of FIG. 1, and FIG. 5 is a diagram of the amplifier of the electronic desk calculator of FIG. 1. FIG. 6 is a waveform diagram of a power supply and audio output signal waveform, FIG. 6 is a waveform diagram of an audio output signal waveform according to a conventional audio output method, and FIG. 7 is a flowchart of processing when outputting a voice synthesized signal. 11... Controller, 15... External R
OMll7...Audio amplification device, 18...
Speaker, 22...Key input device, 25...
・Liquid crystal display device, 31...Built-in only 0M134...
...RAM137... Arithmetic circuit, 50...
D/A converter, 51... impedance conversion circuit.

Claims (1)

[Claims] 1. When outputting an audio signal from an integrated circuit for speech synthesis, a waveform having a predetermined slope from the logic level to the center level is added before and after the audio signal output waveform output from the integrated circuit, and a waveform having a predetermined slope from the center level to the above An audio output method characterized by adding a waveform having a predetermined slope up to a logic level.