JPS6044676B2 - speech synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech synthesis device designed to reduce power consumption in a digital-to-analog (D/A) conversion circuit, and is particularly suitable for application to an integrated speech synthesis circuit. This invention relates to a speech synthesis integrated circuit.

Conventionally, in an integrated speech synthesizer dedicated to speech synthesis, the power supply is turned off in order to reduce power consumption when speech synthesis is not performed.

However, if the same voice synthesis integrated circuit performs numerical calculations, timing, key input, display, etc. in addition to voice synthesis, it is not possible to turn off the power of the entire circuit even when no synthesized sound is output, and therefore the power consumption increases. There was a problem that it was not possible to measure the reduction of The present invention was made in order to eliminate the above-mentioned conventional drawbacks, and in particular, the D/R due to ladder resistance.
When the A conversion circuit is built in and the synthesized analog signal is not output to the outside, the D/D conversion circuit can be converted by setting the input potential of each bit of the ladder resistor equal to the potential connected to the least significant bit.
It is an object of the present invention to provide a speech synthesis device that reduces power consumption in an A conversion circuit.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of a speech synthesis calculator which is an embodiment of the device of the present invention.

In the figure, reference numeral 1 denotes a controller (VC) that performs voice synthesis and other controls, which is composed of a one-chip LSi, and this controller is equipped with various external connection terminals.

Terminal A is an address bus line, D is a data bus line,
CE is a chip enable signal line to which a memory 2 (for example, read-only memory ROM) is connected externally. DA is an audio signal output line and is connected to the audio amplification device 3. A speaker 4 is connected to the output line of this AMP3. Further, F is a terminal of a port that outputs a signal for power control of AMP3 to AMP.T is a strobe signal output line, and T is a key return signal line, which is connected to the key input device 5. Further, H is a common signal line, and S is a segment signal line, which are connected to a display device 6 consisting of a liquid crystal display device (DISP).A memory 2 consisting of the above-mentioned ROM is used to operate as a calculator. The main program and audio data for VC are pre-stored.
Controller 1 has read-only memory (RO
M), a read/write memory (RAM), an arithmetic control circuit, etc. are built in, and a speech synthesis control program is stored in advance in this read only memory. The VC controller 1 has versatility as a controller for speech synthesis equipment. In other words, even if the devices are different, the words of the synthesized voice to be output are different, and the specifications are different, the contents of the external memory 2 (for example, ROM) can be changed, the key top display can be changed, and the segments of the display can be changed. The controller C itself can be used without any changes, just by changing the configuration. FIG. 2 is a block diagram showing a specific system configuration of the VC controller 1. As shown in FIG.

In the figure, 10 is a read-only program that stores an algorithm (processing program) for voice synthesis control in advance.
It is a memory with a capacity of 16 bits and 512 steps.

A1 to Al4 are address signal terminals that output address signals to the external ROM memory (Fig. 1 and 2), and D1 to D
8 is a data signal terminal for reading data from an external ROM. 11 is a program counter (PC), 12 is a data pointer (DP), and the program counter 11 is a counter that indicates the address for voice synthesis control in the built-in ROM1O and the address of the main program in the external ROM.

On the other hand, the data pointer 12 is a pointer that indicates the location (address) of the audio data stored in the outer memory. 13 is a read/write memory (RAM), which has a capacity of 8 bits x 64 = 512 bits and includes an area used for voice synthesis control, an area used for calculator calculations, and an area for display. be.

Each bit in the display area corresponds to each segment of the display device 6 (for example, an LCD display), and by writing a display pattern in this area, the pattern is displayed. 14 is an address register of RAM13.

A certain area of RAM 13 may be used as a stack for a subroutine, and numeral 15 is a stack pointer (SP) indicating the position thereof. Reference numeral 16 denotes an arithmetic unit (ALU) that performs arithmetic and logical operations on internal data path signals, signals output from the built-in ROM1O, and signals output from the accumulator A 17.

Reference numeral 18 designates a discriminating flip-flop Jll9 a carry flip-flop (half-carry one) from the 4th bit, and reference numeral 20 a carry flip-flop C. 21 is an instruction decoder, which has a built-in ROM1O
It decodes the upper 8 bits of the opcode output from and outputs the micro order.

22 is a power control section, which controls oscillation or stopping of the clock generator 23 and generating/generating the system clock.
Controls such as stopping and turning on/off the power for display.

That is, during the operation, system clocks φ1 and φ2 are output, and the entire system operates. Furthermore, in the displaying state, only the display control section is operated by stopping the generation of the system clock. Since this LSi is composed of C-MOS, the system clock. By stopping the power consumption, power consumption can be kept low. Cc is the negative power supply terminal of this LSi. CGl and CG2 are terminals to which a resistor or ceramic filter for oscillating the built-in clock generator 23 is connected. By the way, this oscillation frequency is 131KHz. 24 is an oscillator (0SC) for the clock function, and this oscillation waveform is transmitted by frequency divider 2.
The frequency is divided by 5.

Xl and X2 are terminals for connecting a crystal oscillator.
The input of frequency divider 25 is a program logic array (P
LA) and a built-in clock generator 2.
3. The output of one of the oscillators 24 is divided. The final stage of the frequency divider 25 outputs a 1 second signal (1S). 26 is a common signal generation circuit (
BP), and H1 to H4 are common signal output terminals. The common signal generating circuit BP also outputs an address signal for the display area of the RAM13. Further, 27 is a buffer (SB) for generating segment signals to the liquid crystal display device.
S1 to S25 are terminals connected to segment terminals of the liquid crystal display device. 28 is a 6-bit input port (Kl)
A key input device (FIG. 1, 5) is connected to K, to K6, and a key return signal is input.

29 is an 8-bit output port (Ti), T1 to T
A key input device is connected to 8, and a key strobe signal is output.

30 is a 4-bit output port (Fi), and in this embodiment, the most significant bit signal of the outer m selection 0M head address signal is output from F4.

31 is a latch circuit for latching 8-bit audio data output from the arithmetic unit 16 (ALU).

32 is a D/A converter, and DAi is a terminal for outputting an analog audio signal.

33 is an impedance conversion circuit, and terminals DAl and D
By connecting a feedback resistor (FR in FIG. 6, which will be described later) between AO and AO, the speaker can be driven by simply connecting a simple amplifier circuit to the outside.

CEO is a terminal that outputs a chip enable signal to the external ROM. Although not shown, the two or more chips in which the chip enable signal generating circuit operates on a micro-order basis are the specific configuration of the controller VC, and the operation will be described below.

Figure 3 shows the built-in ROM memory (second
10) and an external ROM memory (see FIG. 1 and 2).

The above built-in BOMlO is 16 bits long and has address 0.
It occupies the area from 000 to 01FF. The external ROM 2 is 8 bits long and can use the area from addresses 0000 to 7FFF. VP in built-in ROM1O is a voice synthesis control program, and external ROM2 is a main program for functioning as a calculator, D1 and VD2.
indicates the storage area of audio data, respectively. The aforementioned program counter 11 (PC) specifies the address of the P and MP program areas, while the data pointer DP specifies the address of the entire area of the outer m selection 0M. That is, when reading data from an external ROM, the data pointer 12
The address information of the data to be read is set in (DP) and the contents of the ROM are read. As seen above, when executing program commands or main program commands for voice synthesis control, the value of the program counter 11 (PC) is counted up each time the step command specified by the program counter 11 (PC) is executed. and execute them sequentially.

Since the speech synthesis control program has a long step of 16 bits, speech synthesis requiring high-speed calculation can be performed even with a relatively slow system clock. The upper 8 bits are an operation code, which is output to the instruction decoder 21 as shown in FIG.
The bits are operands and are output to the internal data bus. On the other hand, instructions read from the external ROM are input internally from the external data bus to the instruction decoder 2.
1 is input. Data is also input to the internal data bus. Additionally, a RAM can also be connected externally. Like the Gaikanzawa 0M, it can be used by sharing the address bus and data bus and outputting the chip enable signal and read line signal from the F port to the RAM. FIG. 4 is a flowchart showing the processing procedure of the entire apparatus. By executing the main program in Sotomazawa0M, processing such as key identification, calculation, and display of calculation results is performed.
When performing voice notification, the word code corresponding to a predetermined word is loaded into the accumulator and the voice synthesis control program is hejumped (subroutine).
A voice announcement of the word is made. FIG. 5 is a block diagram of a block incorporating a D/A converter and an impedance conversion circuit, which are the features of the present invention.

In the figure, PV1-PV8 are digital audio signal latch circuits, the outputs of which are connected to ladder resistors 2R, R via gates G1-G8 and buffers B1-B8. This ladder resistor is constructed of a diffused resistor to obtain high accuracy. This output DAi is connected to the outside from a terminal of the LSi. Therefore, the speaker can be driven simply by connecting an ordinary amplifier circuit. Further, an impedance conversion circuit consisting of an inverter circuit is provided at the output of the D/A converter. In this conversion circuit, A
is an inverter circuit, and by connecting a feedback resistor FR between its input and output, this inverter circuit is used as a linear amplifier. Since the resistance R of the D/A conversion circuit is approximately several tens of kilohms (for example, R = 30 kilohms), the output impedance of the D/A conversion circuit is quite high. Its output impedance is lowered. For this reason, the current can be taken out to the outside, and the
As shown in the figure, a speaker can be driven using a very simple emitter follower circuit. Note that the NAND gates G1 to G8 provided at the input of the D/A conversion circuit are controlled by the signal Amp. This signal Amp is Mw=
It is generated based on the logic of F1(ACL+ST)θ. F with this)
1 is a signal for turning on the amplifier power supply as described above (also output from port F1), ACL is a signal indicating an auto clear state, and ST is a signal indicating a displaying state. That is, if audio is being output and the state is not in the auto-clear state but in the calculation state, the NAND gate operates as a clock gate,
The contents of the latch circuit PVi are D/A converted. In other cases, the NAND gate output becomes “H”, so the D/A
The input voltage of the conversion circuit becomes "L". Therefore, no current flows through the ladder resistor, and unnecessary power consumption is avoided. On the other hand, the impedance conversion circuit is controlled by this Amp signal. Inverter 11 Analog switch AS..MO
The S transistor gate PM is this control circuit. If this control circuit were not present, the input of inverter circuit A would be “
Since the output becomes ``H'' when the output is ``L'', a current flows through the feedback resistor FR.In other words, when no audio output is performed, power is wasted. By inserting a control circuit like this, wasteful power consumption can be eliminated.In other words, when the Amp signal is "L", the analog switch AS becomes 0FF, and the input of the inverter circuit A becomes "H" potential. , the potential of DAO becomes ``L'', and no current flows through the feedback resistor FR.Furthermore, when the circuit shown in Fig. 7 is connected, the transistor turns OFF, and no unnecessary current flows through the speaker.Explained above. As described above, according to the present invention, when synthetic sound output is not performed, power consumption in the D/A converter can be eliminated,
This has advantages such as being able to reduce the overall average power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a speech synthesis calculator which is an embodiment of the speech synthesis device according to the present invention, FIG. 2 is a specific block diagram of a controller (VC) in the same block diagram, and FIG.
The figure shows the address relationship between the built-in ROM and the outer memory 0M.
FIG. 4 is a flowchart showing the processing procedure of the entire apparatus, FIG. 5 is a block diagram of a block including a D/A converter and an impedance converter, and FIG. 6 is a speaker drive circuit diagram using an emitter follower. In the figure, 1: controller, 2: memory, 3: amplifier circuit, 4: speaker, 5: input device, 6: display device, 10:
Built-in ROM, 13: RAM, 16: Arithmetic circuit, 31: Latch circuit, 32: D/A converter, 33: Impedance conversion circuit.

Claims (1)

[Claims] 1. A device that is equipped with at least means for synthesizing synthesized sound as a digital audio information signal, and a D/A conversion circuit having a ladder resistance for digital-to-analog conversion of the digital audio information signal, and outputs the synthesized analog audio signal to the outside. In this case, a gate circuit is provided to make each bit input potential of the ladder resistor of the D/A conversion circuit equal to the potential connected to the least significant bit side when the synthesized analog signal is not outputted to the outside. Characteristic speech synthesizer.