JPS6045451B2 - Digital control circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital control circuit testing device for semiconductor memories and the like.

2. Description of the Related Art As a testing device for semiconductor memories, etc., there is a known device that uses a trigger pulse as a starting input to form a test pattern according to a predetermined program.

This test equipment is activated by a trigger pulse and forms a test pattern according to an internal program. Therefore, for example, as in semiconductor memory, different operating cycles such as a write cycle and a read cycle are used. In one embodiment, the operating period is determined after the trigger pulse occurs. Therefore, it is impossible to match the period of the trigger pulse with the operation period. That is, the trigger pulse generation circuit described above is
This is because, since it is generally configured with a program counter that receives a reference pulse as input, it is necessary to preset information for determining the period when a trigger pulse is generated.

For the above reasons, in the test apparatus having the above configuration, when the operating cycle changes, the test is not performed using that cycle as a dummy cycle, but the test is performed in the next cycle.

For this reason, there was a problem in that a test pattern in which writing and reading were performed alternately took a long time.

In this invention, in the pattern generation circuit, after a trigger pulse is input, a test pattern (synchronization pulse) is actually generated.
Focusing on the fact that it takes a considerable amount of time (for example, about 120 nsec) until it is output, and using this delay time,
The purpose is to improve test efficiency by matching the period of the synchronizing pulse that determines the period of the test operation with the operation period required for the test and inputting it to the device under test.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1 denotes a pattern generation circuit which uses the sum of trigger pulses as a starting input to form a test pattern according to a predetermined program.

This test pattern is composed of a synchronization pulse SYNC having the same period as the trigger pulse and a pattern signal used as a test input signal, and the trigger pulse has a delay time t1 with respect to °C. 2 is a device under test, which is, for example, a digital control circuit such as a semiconductor memory.

Reference numeral 3 denotes a shift register group, which is composed of shift registers with a 3-bit configuration that receives the respective pattern outputs of the pattern generation circuit 1 as inputs.

One of the above shift register groups is shown in the same figure,
It is composed of cascade-connected flip-flop circuits 3a to 3c, and the same applies to other shift registers. Reference numeral 4 denotes a clock pulse generation circuit, which inputs the trigger pulse TG and delays it by delay means 4a to 4c, thereby generating the clock pulse φ1 of the shift register 3.
~ form φ3.

The relationship between the delay time T4 of the clock pulses φ1 to φ3 with respect to the trigger pulse m and the delay time t1 of the synchronization pulse SYNC with respect to the trigger pulse TG is directly related to the pattern signal outputted via the shift register 3. In order to match the synchronization pulses supplied to the device under test 2, the following relationship is set. 5
is an oscillator circuit that forms a reference pulse.

6 is a trigger pulse generation circuit, which meets the above criteria. Consists of a program counter that receives pulses as input.

Reference numeral 7 denotes a gate circuit for switching the preset input of the program counter 6, and among the shift registers, those that receive a pattern signal that can determine the test operation cycle (for example, in the case of semiconductor memory, write The control signal generation circuit 8, which receives the intermediate output of the /read command), selects either 9a or 9b in the register in which preset information for the program counter 6 that determines the period of the trigger pulse is written. It is sent to the program counter 6 mentioned above.

In this embodiment, at the time when the trigger pulse TG is generated, the pattern output formed by the trigger pulse TG does not have a test operation period known, and at that point, the program counter has a period determined by the previous preset information. Focusing on the fact that the pattern signal is operating as a device and that there is a time delay before the pattern signal is actually output, we decided to further delay the pattern output using a shift register before sending it to the device under test. At the same time, this time is used to determine the operation test cycle based on the pattern output and to correct the cycle of the trigger pulse BI° C. in order to match the synchronization pulse SYNC and the pattern output. This will be explained in detail with reference to the operational waveform diagram in FIG. The operating cycle of the device under test 2 is a read cycle T, such as a semiconductor memory, for example.
When there are two types, R and write period Tw, preset information forming the read period TR is written in the register 9a, and preset information forming the write period TW is written in the register 9b.

At the start of the test, when the gate circuit 7 operates to input the output of the register 9a to the program counter 6, and the pattern signal formed by the trigger pulse m is for writing, the following is done. Corrections will be made.

Upon generation of the first trigger pulse TG, the pattern generation circuit 1 outputs the synchronization pulse SYNC and the pattern signal POUT with a delay of time t1.

On the other hand, the clock pulses φ1 to φ3 of the shift register 3 are generated with a delay of time T4 to the trigger pulse TG. Since these first clock pulses φ1 to φ3 are generated prior to the synchronization pulse, the pattern output input here is processed as an invalid signal. That is, the write command W is set in the first flip-flop 3a by the second clock pulse φ1. After this, write command w to this first flip-flop 3a
Since is set, the gate control circuit 8 switches the gate circuit 7 to transmit the contents of the register 9b to the program counter 6. Therefore, when the third trigger pulse is generated, the write cycle information Tw is set in the program counter 6, and the cycles of the third and fourth trigger pulses TG are set as the write cycle Tw.
Correct it to

On the other hand, the second flip-flop 3b constituting the shift register receives the first and second clock pulses φ2.
Since the input is invalid at the timing , the write pattern w is set at the third clock pulse φ2, and the output Rb is obtained.

The period of the clock pulse of this flip-flop 3b is
The period of the trigger pulse is corrected and matches the content of the pattern signal.

Similarly to the above, the output stage flip-flop 3c constituting the shift register receives an invalid input at the timing of the first and second clock pulses φ3, so the write pattern W is input to the output stage flip-flop 3c at the timing of the third clock pulse φ3. φ3
to form the output Rc. This output Rc is a pattern signal for writing, and its output period matches that modified for writing of the synchronization pulse SYNC, which is input directly to the device under test 2 without passing through the shift register 3. is obtained. In order to clarify the relationship between this pattern output Rc and the synchronizing pulse SYNC, the synchronizing pulse SYNC is rewritten as shown in the figure. Note that when the second pattern output of the pattern generation circuit 1 is a read command, the read command R set by the fourth clock pulse φ1
Since the gate circuit 7 is switched to the register 9a, the contents of the register 9a are set in the program counter 6 at the timing of the fourth trigger pulse m, and the fourth and fifth cycles are read out. The synchronizing pulse SYNC is corrected to the desired period TR, and the synchronizing pulse SYNC is made to match the pattern output while being outputted through the shift registers 3b and 3c.

The operation of the program counter 6 is such that the content of each digit of the binary counter becomes "1" and a trigger pulse is generated, and when the content is reset by the next reference pulse, the content is one of the above. A preset operation is performed by determining the contents of register 9a or 9b.

Thereafter, the period is similarly corrected according to the content of the pattern output, and the synchronization pulse SYNC and the pattern output match, so that the test efficiency can be improved. That is, according to this embodiment, the synchronization pulse SY
Only the first two cycles of NC become dummy cycles, and after that a continuous repeating pattern signal can be formed.

This invention is not limited to the above embodiments, and can take various embodiments.

Although the phase relationship of the clock pulses φ1 to φ3 used for the above-mentioned time adjustment and period correction can be changed to some extent, in order to reduce the number of dummy cycles and the number of bits of the shift register, it is necessary to change the phase relationship as shown in the above embodiment. Something is desirable.

In addition, although the delay means for forming the clock pulses φ1 to φ3 are connected in series, it is also possible to obtain the delay means from those having the above-mentioned times ζ to ζ, or to form them from the output of the program counter. Good too.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is an operation waveform diagram. DESCRIPTION OF SYMBOLS 1... Pattern generation circuit, 2... Device under test, 3... Shift register, 4... Clock pulse generation circuit, 5... Oscillator circuit, 6... Trigger pulse generation circuit (program counter) ), 7... gate circuit, 8
5... Control signal generation circuit, 9a, 9b... Lujistar.

Claims (1)

[Claims] 1. A trigger pulse generation circuit, a pattern generation circuit that generates a test pattern and synchronization pulse according to a predetermined program in response to the trigger pulse, and each test pattern supplied to the device under test of this pattern generation circuit. A clock pulse generation circuit which takes as input, supplies a shift register consisting of a plurality of bits, and a clock pulse delayed with respect to the trigger pulse to the shift register, and the clock pulse supplied to the final stage shift register is , set to be shorter than the delay time in the pattern generation circuit, and the output of the shift register after the first stage but before the final stage of the shift register whose input is the pattern output that determines the operating cycle of the device under test. A digital control circuit testing device comprising: a trigger pulse cycle control circuit that controls the cycle of the trigger pulse.