JPS6045458B2 - External memory control method for image terminal equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for an external memory of a computer image terminal device.

It is desirable that an external memory used as an image terminal device for a computer has the function of real-time memory for television signals as a device for importing image signals into a computer device (CPU).

For example, N'YSC memory requires high-speed television signal data, that is, the ability to read or write at 93NS or 7ONS per word, and because of the problem of image data capacity, a low-speed, large-capacity MOS is used. A memory system is used that combines a main memory composed of memory devices and an associated high-speed, small-capacity buffer memory. In this system, two sets of buffer memories are used to alternately write at TV speed and transfer to main memory at low speed, thereby converting the data transfer speed within the memory system. . In such a memory system, a plurality of pieces of data are stored in a buffer memory by sequential writing, and then transferred all at once to the main memory.
On the reading side, this process is reversed to obtain data that matches the TV speed. In this case, it is generally difficult for the CPU to specify an arbitrary address on the memory area and read or write data continuously.

However, with the CPU, it is possible to access the data of only one pixel or only a certain part of the TV image, but in this case, the specified addresses are generally discontinuous, so for the reasons mentioned above, continuous access is not possible. difficult. According to the present invention, a start address and an end address specifying a desired access area are sent from the CPU to the external memory, and then an external memory operation start pulse is sent.

By sending a setup pulse, it is possible to make one continuous access to the desired area. At this time, the data ready pulse is sent from the external memory to the CPU so that it remains valid while the data matching the desired address is sent from the buffer memory, and the CPU takes the data within this interval into the internal memory. Correct De; Ichita's CP
Writing to U is executed. When accessing data in only a certain part of a television image, the addresses corresponding to that area are generally discontinuous, so the movement of the address must include discontinuous jumps. However, in external memory, data transfer from the main memory to the buffer memory within the memory system is performed in batches of a certain data width, so the address corresponding to this data width is the address given to the main memory system. must be given as the least significant bit of This address will hereinafter be referred to as AAO5. In the memory system cited in the present invention, 5-bit addresses from AAOO to AAO4 are given to the buffer memory, and addresses from AAO5 to AAl8 are given to the main memory, and all addresses are given to the main memory from AAOO to AAO4.
It consists of 19 bits with AAl8 as MSB and SB. However, since the AAO address is also given as a variable from the CPU, the external memory first finds an address of AAO5 or higher that includes the specified address from the CPU, gives that address to the main memory, and transfers the data to the buffer register all at once. Then, when transferring from the buffer register to the CPU, the timing when AAO4 and below match the specified address is determined as data ready (DRDY).
) is sent to the CPU as a pulse. When accessing only a certain portion of a television image, memory access at the AAO rate is executed once in each of the sections before and after including the address discontinuity point. These operations will hereinafter be referred to as post-processing and pre-processing, respectively. Since the television image signal is input to the external memory in raster format, accessing only a certain part of the image as described above means accessing starting and ending at a point on one raster. It means repeating. Therefore, the address jump occurs n-1 times, and the DRDY pulse is a continuous pulse sent out n times. signal. During the period in which the DRDY pulse is valid, data can be exchanged with the CPU, so in this period, the strobe pulse sent back from the CPU is used to read data from the external memory device, and the pre-processing and post-processing are performed in this period. External mail is available in this section. By using the reference pulse inside the memory device, all data in a specified area can be automatically and continuously accessed only by a trigger operation using a setup pulse from the CPU. Although the above explanation mainly concerns the read mode, completely similar control is performed in the write mode as well. That is, the present invention provides an external memory device used as an image terminal device connected to a computer device, in which the memory device has a small-capacity buffer memory that can be accessed at high speed and a large-capacity main memory that can be accessed at low speed. A computer (hereinafter referred to as C) consists of a combination of memory.
Transfers a certain unit width of data consisting of multiple pieces of data including the address specified by the PU from the main memory to the buffer memory, and retrieves only the data at the specified address within the transferred section. In order to transfer data to the CPU, a read start pulse (hereinafter referred to as setup pulse) and a data transfer start pulse (hereinafter referred to as DRDY pulse) are exchanged between the CPU and external memory, and the specified data is accessed. In the period in which the DRDY pulse is valid, the address generation section of the external memory section is incremented by a strobe pulse from the CPU, and in the period in which it is not valid, the address generation section is incremented by a reference pulse inside the external memory. This is an external memory control method that also uses a method that automatically consecutively accesses data corresponding to rectangular areas on a memory map specified by discontinuous addresses.

In an external memory system connected to a CPU, the present invention exchanges control signals between the CPU and the external memory in order to access data in a portion of the memory with random addressing. It also automatically switches between the strobe pulse sent back from the CPU to the external memory and the reference clock pulse inside the external memory to access partial data on the image. The aim is to automatically perform discontinuous jumps in addresses in response to a reference clock pulse, thereby allowing data in a desired area to be accessed continuously.

The present invention consists of a computer as an image capture device, an interface section with an external memory, and a frame memory used as an image terminal device. circuit, the address generation circuit output and C
It includes a circuit that detects a match with an address specified by the PU and sends a DRDY pulse to the CPU at the matching timing.

Next, the present invention will be explained in detail with reference to FIG. 1, which shows one embodiment of the present invention.

In FIG. 1, image signals written at the scanning speed of a television in a memory section consisting of a low-speed, large-capacity main memory 4, a high-speed write buffer memory 3, and a high-speed read buffer memory 5 are transferred to a read data bus 9 and an interface section 2. Then, they are sequentially written to predetermined addresses within the computer (CPU) 1. Data transfer at this time is normally performed at a speed of 1 to 5 μs/word. Prior to data reading, the address specifying the area to be accessed is in the form of an x address (corresponding to a horizontal line) and a Y address (corresponding to a horizontal line number) as four types of data 14 including a start address and an end address, respectively. It is given to the memory control section together with strobe pulses 12 and 15. The memory control unit includes a memory write/read control unit 6.
and an address generating section 7. Address generator 7 receives setup pulse 1 from CPU1.
Stepping is started using 1 as a starting trigger, and the output address is supplied to the memory section. Immediately after the step is generally the aforementioned preprocessing period, in which data of a certain unit width including the start address designated by the CPU is transferred from the memory section to the buffer memory in a batch. Therefore, when transferring data from the buffer memory to the CPU1, a DRDY pulse 10 is generated by the address generator 7 to indicate that the data is after the CPU specified point.
It is sent to the PU1 side. In the CPU 1, the data after this pulse is sequentially taken into the internal memory of the CPU 1, and access to the data in the desired area is achieved. Further, a mode control pulse 13 is sent from the CPU1 to the memory control section, and the memory control section performs an operation according to the mode.
When writing data from the CPU1 to the memory section, the data is sent from the write data bus 8 to the write buffer memory. In the memory system used in the example,
The number of words collectively transferred to the buffer memory is 18. The address corresponding to this number of words is now assumed to be AAO5.

This AAO5 corresponds to the least significant bit of the address supplied to the main memory 4 within the memory system.
Next, the timing of the transfer mode of one point data to the CPU will be explained with reference to FIG.

In FIG. 2, S1 indicates a clock pulse train used for addresser increment, and only one clock pulse P1 in the pulse train is a strobe pulse from the CPU. S2 is a setup pulse, and at the timing of this pulse, C
The start address designated by the PU is initialized into a counter in the address generator. Thereafter, the counter increments, and at the timing indicated by point A in the figure, control is performed so that address AAO5 is not incremented. S3 indicates the address generator output, and in this case, the designated start address is 66. From point A to point B in the figure, A includes the CPU designated address 66.
The address of this section is given to the main memory, and the data of this part is transferred all at once and sent to the buffer.S4 represents the 18-word-width batch readout.Point B in the figure. The period from to point C is the period in which the data corresponding to the specified address is sent from the external memory, and the DRDY pulse S7 indicating the timing of the specified data
As a result, desired data is taken into the CPU.
In the figure, the tortoise represents the section in which data is transferred from the buffer memory, and S6 represents the data read from the external memory system. S7 indicates the DRDY pulse, S8 indicates the data taken into the CPU, S9 indicates the preprocessing section, SlO indicates the address AAO4, and SIO indicates the address AAO4.
represents address AAO5. The operation of the memory system is shown in detail in Invention 1: External Memory Control Method for Image Terminal Apparatus filed by the same applicant on May 12, 1939.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a timing diagram illustrating a read mode for one point data from an external memory in the embodiment of the present invention. In the figure, 1... computer device for image data processing, 2... interface device between the computer and external memory, 3... high-speed write buffer memory inside external memory, 4... ...Low-speed large-capacity main memory inside external memory, 5...High-speed read buffer memory inside external memory, 6...
...Memory write/read control unit in the memory control unit, 7...Memory address generation unit in the memory control unit, 8...Write data bus from the CPU to the external memory, 9... ... Read data bus from external memory to CPU, 10... External memory to C
Data ready pulse to PU, 11 to 13...CP
Various control pulses from U to external memory, 14...
...Address pulse given from the CPU to the external memory, 15...Strobe pulse for latching the 14 addresses inside the external memory.

Claims (1)

[Claims] 1 A control method for an external memory for a computer image terminal device, which is composed of a low-speed, large-capacity main memory and a high-speed, small-capacity buffer memory, in which data of a predetermined unit width including an address specified by the computer is stored in the main memory. An external memory control method for an image terminal device, characterized in that when data is transferred from a buffer memory to a buffer memory and only specified data within the unit width is retrieved, an address issuing section of the external memory is advanced by a strobe pulse from a computer. .