JPS6145259B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an external memory control system for an image terminal device used as a computer image terminal device.

The memory of an image terminal device is required to have high-speed response and large capacity, and to meet these requirements, the entire memory is often composed of a low-speed main memory and a high-speed buffer memory. in this case,
Accessing data to memory requires two stages: buffer memory and main memory. Therefore, when viewed from a computer device, it is not possible to write or read data by randomly specifying an address in the memory. In other words, the memory configuration described above has the disadvantage that it cannot be used as a random access memory.

In relatively small-capacity memory systems, memory elements with high-speed response can be used as random access memory, but as memory for terminal equipment that handles image signals, the input data is data from a computer. In addition, it is essential to have the ability to capture television signals as well. Considering these conditions, image memory should be a combination of MOS type low-speed large-capacity memory and high-speed small-capacity memory, as described above. is the optimal memory system.

Therefore, an object of the present invention is to provide an external memory control method for an image terminal device that can apparently treat a memory system composed of a low-speed large-capacity memory and a high-speed small-capacity memory as a random access memory. It is to provide.

FIG. 1 shows an embodiment of the present invention, in which a computer section 1, a write data buffer 2 and a write data switch 2' provided attached to an external memory device, and a write data switch 2' also provided attached to the external memory device. read data buffer 3 and read data switcher 3', which constitute the external memory device, high-speed write buffer memory 4, high-speed read buffer memory 5, main memory 6, address generator 7, address from address generator 7, and specified from the computer. and an address comparison section 8 that compares the address with the address. The coincidence output signal of the address comparator 8 is sent to the computer side as a data ready pulse, and at the same time is sent to the data buffers 2 and 3 as a data switching signal. The output address from the address generator 7 is divided into two parts and sent to the main memory and buffer memory parts, respectively. It is also sent to the address comparison section 8 at the same time. The address generator 7 and address comparator 8 are given a designated address from the computer. Further, a setup pulse, which is a start pulse for advancing the address, is applied from the computer to the address generation section to control the start-up of the address generation section.

Next, the operation of the configuration shown in FIG. 1 will be explained. first,
Address information of designated data is sent from the computer 1 via the address bus 12 to the address generator 7 and the address comparator 8, and is latched, respectively. Next, when a setup pulse 13 is sent from the computer, the address generator 7 starts to advance from the pre-latched address at this pulse timing. The generated address is stored in the main memory 6 and buffer memories 4 and 5.
It is divided into two parts and supplied. The memory system cited in the embodiment of the present invention has a memory capacity of 512 x 576 x 8 bits, or 2359296 bits. Here 512 indicates the number of accumulated horizontal lines, 576
indicates the number of sampling points within one horizontal period. Further, 8 indicates that the sampled data appears in the form of an 8-bit parallel code at each sampling point. The number of address bits given to this memory system is 19 bits, of which 5
14 bits are assigned to the buffer memory side and 14 bits are assigned to the main memory side. Furthermore, these
The 19 bits constitute a circular address that repeats every frame period. Therefore, control is performed so that the upper 14 bits are incremented once every cycle of the lower 5 bits. Furthermore, among the lower 5 bits, 2 bits including the least significant bit (LSB) are controlled to advance in ternary notation, and the remaining 3 bits are controlled to increment in hexadecimal notation, so the cycle of these 5-bit addresses is in hexadecimal notation. becomes. This means that the number of data that can be temporarily stored in buffer memory is 18. Alternatively, the upper 14 bits are a pure binary code, which indicates that the half width of the least significant bit matches the cycle time of the 18 data.

Here, the actual data transfer between the buffer memory and the main memory will be explained with reference to FIG. When transferring data from the write buffer memory 4 to the main memory 6, serial input data is transferred to one of the two sets of write buffer registers.
18 words are written, and then the subsequent 18 words are transferred all at once to the main memory within the time period.
The other 18 words of input data within this time period are sequentially written to other buffer registers. In this way, input data is written into the main memory by alternately using the two sets of buffer registers. Also, when reading from the main memory, the 18
This is carried out by collectively transferring words to a read buffer register and sequentially reading out the data one word at a time. In this case as well, batch transfer is performed alternately to two sets of read buffer registers. When such a memory system is used as an external memory of a computer, data at a desired address in the main memory cannot be directly accessed. For example, when reading only one word of data from an external memory and importing it into the computer, 18 words containing the data at that address are read out and transferred from the main memory to a buffer register, and then serially sent from the buffer register. Only the data that corresponds to the desired address among the 18 words contained in the data can be imported into the computer. In the case of reading only one word, 14 bits of the 19 bits of the address corresponding to the data specified by the computer that are given to the main memory indicate the 18 words of data including the data, and the lower 6 bits indicate the data of the 18 words. 1 word, that is, data desired by the computer. Since this data cannot be directly accessed from main memory, it is necessary to control the movement of addresses given to the memory system.

Referring to FIG. 3, _S1 is a set-up pulse sent from the computer, and the address counter in the external memory starts incrementing at this pulse. Assume that the first value of the increment is the address specified by the computer, that is, 30.
Here, the address is incremented and when it reaches 36,
AA04 (MSB of the lower 5 bits) is inverted S ₁₁ , and as a result, the upper 14 bits should be incremented by one step, but the increment of this upper bit is prohibited only once by the pulse of S ₅ . The result was AA05 (top
For bits from 14 bits (LSB) to AA18, the exact same address as when the setup pulse was applied is repeatedly given to the main memory _. on the other hand
The lower 5 bits from AA00 to AA04 are cleared and return to 0, which is the initial value of the cycle. From then until the count is counted up to 18, reading from the main memory, that is, batch transfer of 18 words of data to the read buffer memory is executed.
Since the read address in this section is from 18 to 36, it means that the data including the data at the desired address has been transferred from the main memory to the buffer register, so the next address is from 36 to 5.
During the increment to 4, data from addresses 18 to 36 is serially read out one word at a time from the read buffer register. The address comparator 8 compares the timing of desired data among these serial read data with the address from the computer and the address in the external memory, decodes it, and sends this section back to the computer as a data ready pulse. On the computer side, if data is captured within the period in which this data ready pulse _S8 is valid, reading from the external memory can be executed.

In addition, when writing data from the computer to the external memory, the 18-word section containing the data at the corresponding address is first read from the main memory using the method described above, and the section in which the data ready pulse sent from the address comparator 8 is valid is read out. Send the desired write data 9. The read data from the external memory is written to the write buffer register again via the read side data buffer 3 and the write side data buffer 2. The data switch 2' provided in the data buffer 2 is controlled by a data switching pulse (same as the data ready pulse), and during the period when this pulse is valid, it selects and writes the write data _S9 from the computer. It operates to send to the buffer 4 register.

On the other hand, in the memory section, reading is executed prior to writing, so among the addresses supplied from the common address generation section 7, the addresses used for writing operations are time-consuming compared to the addresses used for reading operations. is late. Therefore, the write address is supplied after being modified (subtracted) by a certain fixed number corresponding to this time difference.

When read data is transferred from the external memory to the computer section, the address and setup pulses are supplied from the computer section to the address generation section 7 and the comparison section 8 and applied to the main memory 6, as in the case of writing. It is controlled so that the least significant bit of the 14 bits is not incremented once, and a certain unit width of data containing the data at the specified address is transferred from the main memory.
The point that data is transferred all at once to the buffer memory on the read side is exactly the same as in the case of writing. A data switching pulse (data ready pulse) 1 sent from the address comparator 8 is transmitted by a data switching device provided in the data buffer that intervenes during data transfer from the buffer memory to the computer.
1, and operates to send out data that matches the designated address and subsequent data as valid data.

At the same time, the data ready pulse is also sent to the computer section, informing that the computer section can internally take in the data after this pulse timing.

As explained above, the present invention uses a read/modify write method to the memory, a data ready pulse from the address comparison section, and a setup pulse for controlling the address generation section in combination to make it possible to handle a large capacity memory that cannot be randomly accessed from the computer's point of view. , it has the advantage of operating in such a way that it can be accessed randomly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing data transfer from a buffer register to main memory, and FIG. 3 is a diagram showing an operation of taking one word into a computer. In FIG. 1, 1...computer section, 2...
...Write data buffer, 2'...Write data switcher, 3...Read data buffer,
3'...Read data switcher, 4...High speed write buffer memory, 5...High speed read buffer memory, 6...Main memory, 7...Address generation section, 8...Address comparison section, 9...Output to external memory Write data bus, 10... Read data bus from external memory, 11... Data ready pulse of address comparison section output, 12... Designated address bus of computer output, 13... Setup pulse of computer output. In FIG. 2, D _a ...indicates input serial data, A,
B, C... each has 18 pieces of data. _m1 ...
...Represents the mode of write buffer register (i). m ₂ ... represents the mode of write buffer register (ii). a...Write buffer register (i)
This indicates that the data column A is written to. b...
This shows that the data B column is written to the write buffer register (ii). c...Indicates that data C column is written to write buffer register (i). T...Indicates that 18 pieces of data are transferred to the main memory at once. In Figure 3, _S1 ...Setup pulse, _S2 ...Address number, _S3
...read address, S ₄ ...represents address count control; in the figure, a high level state indicates count-up execution, and a low level state indicates count prohibition. _S5 ... Upper 14 bits (AA05 to AA18) represent step control; in the figure, a high level state indicates step execution, and a low level indicates step prohibition. S ₆ ...
... Shows main memory read control, and the high level state in the figure represents read execution. _S7 ...
Read data from read buffer register, S ₈ ...Data ready pulse, S ₉ ...Computer import data, S ₁₀ ...Address AA05
(LSB of upper 14 bits), S ₁₁ ...AA04 of address
(MSB of the lower 5 bits), S ₁₂ ... of the address
AA06.

Claims (1)

[Claims] 1. In an external memory device consisting of a combination of low-speed large-capacity main memory and high-speed small-capacity buffer memory, when data is read from the memory device and transferred to the computer, the main memory in the memory Controls the advancement of the least significant bit of the address given to the address, repeats the same least twice at least twice, gives it to the main memory, and stores multiple pieces of data specified by the least significant bit. The data is read out all at once and transferred to the buffer memory on the reading side, and then it is determined whether the address given to the memory matches the address specified by the computer or not, and the data after the matching timing is sent to the computer as valid data. External memory control method for image terminal equipment.