JPS6046449B2 - Division error detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a division error detection method that allows errors in control signals in a division device to be detected with a simple configuration.

Although the control circuit of the division device is complicated, in conventional division devices, a parity bit is provided in the data system, and error detection is performed using this, but a means for checking errors in the control system is provided. It wasn't.

In order to detect errors in the control system, the control system is duplicated.
Although duplication has been practiced, error detection methods using doubling or tripling have the disadvantage of significantly increasing the amount of metal. The present invention is based on the above considerations, and makes it possible to detect errors in the control system of a dividing device by simply adding relatively simple hardware.
The purpose is to provide a detection method.

Therefore, the division error detection method of the present invention is a division error detection method for a division device that performs division by repeating addition and subtraction between a dividend or a partial remainder and a divisor, and is a division error detection method for a division device that performs division by repeating addition and subtraction between a dividend or a partial remainder and a divisor, and is a method for detecting division errors in a division device that performs division by repeating addition and subtraction between a dividend or a partial remainder and a divisor, and is a method for detecting division errors in a division device that performs division by repeatedly adding and subtracting a dividend or a partial remainder and a divisor. a control signal register in which a control signal is set; a first prediction circuit that predicts a quotient to be obtained by the subsequent calculations based on the output of the control signal register; and a comparison circuit that outputs an error signal when the output of the first prediction circuit and the output of the second prediction circuit do not match. It is something to do. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 shows one embodiment of the present invention, in which 1 is an A register storing the dividend;
2 is a D register that stores the divisor, 3 is a 312D register that stores 312 times the divisor, 4 and 5 are shift circuits, 6 is a selection circuit, 8 and 9 are control signal generation circuits,
10 is an adder/subtracter that performs an operation between a partial remainder and an appropriate multiple of the divisor, 11 is a selection circuit that selects either one of the control signal generation circuits 8 and 9 according to the carry output of the adder/subtractor 10, and 12 is a selection circuit. a register storing the output of 11; 13;
14 is a register that stores the partial remainder; 15 is a circuit that predicts the quotient based on the output of register 14; 16 is a prediction circuit that predicts the quotient based on the output of register 14; A comparison circuit, 17 is a register that stores the output of circuit 15, 18 and 19 are carry signal lines,
20 is an error signal line, 21 is a flip-flop that stores the signal value on the carry signal line 19, and 22 is register 1.
7 and a flip-flop 21 are used to correct the quotient, 23 is a register that stores the true quotient output from the correction circuit 22, and 24 is a decoder.

Note that the signal on the carry signal line 18 becomes R1 when there is no carry, the signal on the signal line 19 becomes RL when there is a carry, and the signal on the signal line 20 becomes R1.
6 detects a mismatch, it becomes r1. Next, the operation of the embodiment will be explained. In the first processing, first, only the beginning of the dividend is sent to the control signal generation circuits 8 and 9, and then only the dividend is input to the adder/subtractor 19. As a result, a signal is generated on the carry signal line 18, and the control signal generating circuit 8 is selected by this signal. The output of the selected control signal generating circuit 8 or 9 is set in the register 12. Next, the multiple of the divisor and the dividend determined by the contents of the register 12 are input to the adder/subtractor 10, where addition or subtraction is performed, and the resulting partial remainder is set in the register 14. Note that the register 12 controls the shift amount of the shift circuits 4 and 5, controls the selection circuit 7, and performs addition/subtraction of the adder/subtractor 10.
This is used to give instructions such as subtraction. The upper bits of the partial remainder are input to circuit 15, which predicts the quotient. Note that the output of the register 2 is also input to the circuit 15. The predicted quotient is stored in register 17. Further, the partial remainder of the register 14 is sent to the shift circuit 4.
The leading portion of the output of shift circuit 4 and the leading portion of an appropriate multiple of the divisor are sent to control signal generating circuits 8 and 9. Note that the control signal generation circuits 8 and 9 are always sent the leading part of the divisor. One of the control signal generation circuits 8 and 9 is selected depending on the sign of the carry signal lines 18 and 19, and the output of the selected control signal generation circuit 8 or 9 is stored in the register 12. The quotient stored in the register 17 is compared with the predicted quotient based on the contents of the register 12, and when the two do not match, an error signal is output. In the second process, the multiple of the divisor specified by the register 12 and the output of the shift circuit 4 are input to the adder/subtractor 10.

The adder/subtractor 10 performs addition or subtraction according to the specification of the register 12, and the partial remainder that is the result is stored in the register 14.
is set to The upper part of register 14 is sent to circuit 15. Circuit 15 predicts and stores the predicted value in register 1.
Send to 7. On the other hand, the output of register 12 is sent to circuit 13, by which the quotient is predicted. The quotient predicted by the circuit 13 and the quotient predicted by the circuit 15 are input to a comparison circuit 16, and the comparison circuit 16 outputs an error signal when the two do not match. The partial remainder of register 14 is
As in the first time, the beginning of the partial remainder and the beginning of the divisor are sent to the shift circuit 4, and the beginning of the partial remainder and the beginning of the divisor are sent to the control signal generation circuits 8 and 9, and the control signal generation circuit 8 selected according to the carry signal. The output of or 9 is stored in the register 12, and preparations are made for the third processing. The above-described processing is repeated a desired number of times after the second processing, and then known post-processing is performed. The embodiment shown in FIG. 1 will be explained in more detail.

Using the multiple divisor method, the upper three bits of the dividend (DIVIDEND) and the divisor (DIVIDER) are decoded to determine the multiple divisor, the amount of shift of the dividend, and the quotient. This method itself is known. FIG. 2 shows the code and pattern, FIG. 2a shows the case where the partial remainder is positive, and FIG. 2b shows the case where the partial remainder is negative. In Figure 2, (Note 1)
indicates the case where the carry of the operation result is 0, and (Note 2) indicates the case where the carry of the operation result is 1. The quotient in Figure 2 is called the temporary quotient. The output of the decoder 24 generates a shift amount for the shift circuit 4, a shift amount for the shift circuit 5, and a control signal for the selection circuit 7.
are doing. The shift circuit 4 is controlled by a 1-bit signal called AINP, and the shift circuit 5 and selection circuit 7 are controlled by a 3-bit signal BINPO, B.
There are signals called INP1 and BGATE. The shift circuit 4 operates as follows by ANIP. 1AINP=0
In this case, shift 2 bits to the left.

If 2AINP=1, shift to the left by 3 bits.

Furthermore, the shift circuit 5 and the selection circuit 7 operate as shown in FIG. 3 due to BINPO, BINP1, and BGATE. The correspondence relationship between the multiplication divisor and the above control signal is as shown in FIG. Furthermore, the correspondence between the tentative quotient and the multiplication divisor is as shown in FIGS. 2 to 5. Therefore, the comparison relationship between the temporary quotient and the control signal is as shown in FIG. 6, and according to this logic, the prediction circuit 13 generates the temporary quotient based on the control signal. On the other hand, the prediction circuit 15 calculates the partial remainder based on FIG.
That is, a temporary quotient is generated from the upper three bits of the register 14. The above also means that a control signal can be created from the partial remainder.

FIG. 7a shows a time chart when a control signal is generated from a partial remainder, and FIG. 7b shows a time chart when a control signal is generated from a partial remainder.
A time chart is shown in which control signals are generated by the control signal generation circuits 8 and 9 in parallel with the generation of control signals by the control signal generation circuits 8 and 9.
When the control signal is generated from the partial remainder as shown in FIG. 7a, it takes an extra time of TI compared to FIG. 7b. Therefore, the control signal generation circuits 8 and 9 generate the control signal in parallel with the generation of the partial remainder by the adder/subtractor 10. According to the embodiment shown in FIG. 1, it is possible to detect errors in the control signal generation circuits 8 and 9, the selection circuit 11, and the register 12, that is, in the generation of the control signals AINP, BINPO, BINP1, and BGATE. Furthermore, errors in the prediction circuit 15, that is, in creating a temporary quotient, can also be detected. In the embodiment shown in FIG. 1, the parts other than the circuit 13 and the comparison circuit 16 also include a conventional division circuit.

In FIG. 1, control signal generation circuits 8 and 9, selection circuit 1
1, the register 12, the decoder 24, etc. constitute a control system of the division device, and in this embodiment, errors in this control system can be reliably detected. Generally, since the adder/subtractor 10 has a parity check function, the quotient predicted based on the output of the adder/subtractor 10 is expected to be correct. It is possible to detect errors in the control system by comparing the When the control system is duplicated, two control signal generation circuits 8 and 9, two selection circuits 11, two registers 12, and two decoders 24 are required, but in the embodiment shown in FIG. 1, only the circuit 13 and the comparison circuit 16 are added. This allows errors in the control system to be detected reliably. As is clear from the above description, according to the present invention, it is possible to detect errors in the complicated control system of the dividing device by adding only a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the upper three bits of the dividend and divisor, the multiplication divisor, the dividend, and the quotient, and FIG. 3 is a diagram showing the control signal and the shift circuit 5. FIG. 4 is a diagram showing the relationship between the multiplication divisor and the control signal, FIG. 5 is a diagram showing the relationship between the temporary quotient and the multiplication divisor, and FIG. FIG. 7 is a time chart when a control signal is generated from a partial remainder, and the control signal is generated by the control signal generation circuits 8 and 9 in parallel with the generation of the partial remainder by the adder/subtractor 10. It is a figure which shows the time chart when creating. 1... A register that stores the dividend, 2...
...D register for storing the divisor, 3...31
2D register that stores 312 times the divisor, 4
and 5...shift circuit, 6 and 7...selection circuit, 8 and 9...control signal generation circuit, 10...computation of partial remainder and appropriate multiple of divisor An adder/subtracter that performs 1
1... A selection circuit that selects either one of the control signal generation circuits 8 and 9 according to the carry output of the adder/subtractor 10, 12... A register that stores the output of the selection circuit 11, 13... . . . A prediction circuit that predicts the quotient based on the output of register 12, 14 . . . A register that stores the partial remainder, 15 . Circuit, 16...Circuit for comparing the outputs of circuits 13 and 15, 17...Circuit 15
18 and 19...Carry signal line, 20...Error signal line, 21...
. . . Flip-flop for storing the signal value on the carry signal line 19, 22 . . . A correction circuit for correcting the quotient by the register 17 and the flip-flop 21, 2
3...Register for storing the true quotient output from the correction circuit 22, 24...Decoder.

Claims (1)

[Claims] 1. A division error detection method for a division device that performs division by repeating addition and subtraction between a dividend or partial remainder and a divisor, and a control signal register in which a control signal for controlling a subsequent operation cycle is set; a first prediction circuit that predicts a quotient obtained by the subsequent operation based on the output of the control signal register; and a second prediction circuit that predicts a quotient from the partial remainder obtained from the subsequent operation. A division error detection method comprising: a prediction circuit; and a comparison circuit that outputs an error signal when the output of the first prediction circuit and the output of the second prediction circuit do not match.