JPS6046450B2 - High-speed buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed buffer memory control method, and particularly to a high-speed buffer memory control method for controlling a buffer memory control section included in an information processing device.

Generally, a high-speed buffer memory constitutes a memory hierarchy, is provided in an information processing device, and retains part of the information stored in the main memory. When this information processing device accesses necessary instructions and operands when executing a program, it first checks whether the desired information exists in the high-speed buffer memory (HIT
), this desired information is supplied from a high-speed buffer memory. However, if the desired information is not present in the fast buffer memory, the information is registered in the fast buffer memory for future use as soon as it is supplied from main memory. When executing a program in an information processing device, the higher the HIT rate to the high-speed buffer memory, the shorter the execution time of the program.

Programs executed by an information processing device include privileged programs and non-privileged programs, and in general, privileged programs have a low HIT rate and non-privileged programs have a high HIT rate. A conventional high-speed buffer memory control method includes one buffer memory control unit and a control flag register that stores a corresponding control flag, and sets a load instruction signal included in the control flag before executing a program. When this load instruction signal is set, the program is transferred from the main storage device to the buffer memory control section, and then this program is executed.

When such programs are executed sequentially, when the preceding program finishes executing, the subsequent program is loaded and executed.

Therefore, the HI level immediately after switching the program to be executed
T rate is very low. This is natural because the storage areas of the main storage device for the programs before and after switching are different. That is, the conventional high-speed buffer memory control method has the disadvantage that the HIT rate decreases when switching programs.

An object of the present invention is to maintain the HI
An object of the present invention is to provide a high-speed buffer memory control method in which the T rate does not decrease.

That is, an object of the present invention is to load the contents of a program to be executed next to an information processing device from a main memory into a high-speed buffer memory that is provided with two sets of high-speed buffer memories and is not currently being used by the information processing device. It is an object of the present invention to provide a high-speed buffer memory control method that can improve the HIT rate when programs are switched.

That is, an object of the present invention is to provide two sets of high-speed buffer memories in an information processing apparatus, and to make the following information available to the currently unused high-speed buffer memories by the information processing apparatus under a control flag indicating the operating status of the high-speed buffer memories. An object of the present invention is to provide a high-speed buffer memory control method that improves the HIT rate when control is transferred to a program by loading program information to be assigned to an information processing device for execution from a main memory. The high-speed buffer memory control method of the present invention is a high-speed buffer memory control method for an information processing device that has a built-in high-speed buffer memory and is configured to temporarily transfer the contents of a main storage device to the high-speed buffer memory for use. , a program comprising two sets of the above-mentioned high-speed buffer memories, and under a control flag indicating the operating state of the high-speed buffer memories, execution is assigned to the high-speed buffer memory that is not currently being used by the information processing device, and then to the information processing device. information is transferred from the main memory, and when control is passed to the program, the high-speed buffer memory is controlled to be used.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. So, the second
1 is an explanatory diagram illustrating the information stored in the control flag register shown in FIG. 1, and FIG. 3 is an explanatory diagram illustrating the operation of the embodiment shown in FIG. 1.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 3. In FIG. 1, the information processing device includes two buffer memory control units A and B and a control flag register 1.

These buffer memory control units A and B each include a high speed buffer memory. Control flag register 1 is
As shown in Fig. 2, control flags A and FB corresponding to buffer memory control units A and B are stored, respectively, and these control flags FA and FB are enabled or not, respectively. Signals EA, EB and buffer memory control unit A currently used by the information processing device.
In-use display signals UA, UB indicating whether the
It has load instruction signals LA and LB that indicate whether to instruct the start of loading the information stored in the main memory into the high-speed buffer memory for the next program to be executed. FIG. 3 shows the program execution request and execution state, the use state of the buffer memory control unit, and the storage state of the control flag register L in the embodiment shown in FIG. In FIG. 3, if there is no program execution request to the information processing device, the system program SP is in a state of waiting for an execution request.

In this state, the program Pl stored in the main memory
, P2, and P3 are executed in this order, so program P1
When there is an execution request, the system program SP sends an enable signal EA and an in-use indication signal UA to use the buffer memory control section A before starting the execution of the program P1.
is set to "゜1" and the program moves to execution of program P1.

When an execution request for program P2 comes during execution of program P1, control is temporarily transferred to system program SP, which executes program scheduling, etc.
If it is decided to execute the program P2 after the execution of the program P2 is completed, the information for executing the program P2 is loaded into the buffer memory control unit B using main memory access during the execution of the program P1. The enable signal EBl and the load instruction signal LB are set to "1".

At the end of program P1, control is transferred to system program S.
Move to P, enable signal EA, and in-use display signal U
At the same time, the in-use display signal I for using the buffer memory control unit B loaded with information for the program P2 for executing the program P2 is set, and the load instruction signal LB is reset.

During execution of program P2, when an execution request for program P3 comes, control is transferred to the temporary system program SP in the same way as above, and while program P2 is being executed, information to be used in execution of program P3 is loaded into buffer memory control unit A. Enable signal EA and load instruction signal L
Set A.

At the end of program P2, enable signal EB and in-use display signal UB are reset, and in order to execute program 3, load instruction signal LA is reset, and in-use display signal UA is set.

In FIG. 3, the operation of the embodiment shown in FIG. 1 will be described assuming that program P2 is executed. Program P
The enable signal EB and the in-use display signal I are set because the buffer memory control unit B during execution of No. 2 is being used.

When a request to execute program P3 comes during execution of program P2, if system program SP decides to execute program P3 at the end of program P2, program P3 is The base indicating the storage start position and the bound indicating the storage size are stored in the base bound register 3, and the system program SP is stored in the instruction counter 2.
sets the value and sets the enable signal EA and load instruction signal LA in the control flag register 1.

As a result, the buffer memory control unit A adds the base stored in the base bound register 3 and the address stored in the instruction counter 2 using the address adder 4, stores the result in the address register 7, and stores the result in the main memory. access. Here, the upper bits of the address register 7 are stored in the high-speed buffer memory directory section 8, and the information read from the main memory is stored in the high-speed buffer memory storage section 9.
Store in.

The instruction counter 2 is counted up by the number of read words each time the main memory is accessed.

The counter 6 is for detecting whether information read from the main memory has been stored in all entries of the high-speed buffer memory, and is incremented every time the main memory is accessed. This operation continues until one of the following conditions occurs: (1) Base bound register 3
When the comparator 5 compares the bound stored in the instruction counter 2 with the address stored in the instruction counter 2, and the address ≧ the bound.

(2) When the content of the counter 6 reaches "1".

That is, when all entries in the high-speed buffer memory are loaded with information read from the main memory. (3) When the load instruction signal LA is reset. When any of the above conditions occurs, the control unit 10 is notified and the loading operation of information read from the main storage device is stopped. At the end of execution of program P2, system program SP resets enable signal EB and in-use display signal I to invalidate all information stored in buffer memory control section B, and then loads it to execute program P3. The instruction signal/signal LA is reset and the in-use display signal UA is set.

This means that the program loading of the buffer memory control section A is finished and the buffer memory control section A is used for executing the program P3. Then, the entry point of the program is set in the instruction counter and control is transferred to program P3. When a request to execute the next program to be executed successively comes during the execution of program P3, the information of the subsequent program is sent using the same means as described above using the buffer memory control unit B during the execution of program P3. Load.

It goes without saying that when main memory requests for loading program information currently being executed and program information to be executed next occur simultaneously, the currently executing program is given higher priority.

The high-speed buffer memory control method of the present invention loads information for the next program to be executed from the main memory into an unused high-speed buffer memory while a certain program is currently being executed in an information processing device. When control of the program is transferred, the HIT rate to the high-speed buffer memory increases, which has the effect of improving system performance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the storage state of control flags in the control flag register shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. 2 is an explanatory diagram of the operation of the embodiment shown in FIG. 1. FIG.

1... Control flag register, A, B...
・Buffer memory control unit, 2...Instruction counter, 3...Base bound register, 4...
・Address adder, 5... Comparator, 6...
...Counter, 7...Address register, 8...
...High-speed buffer memory directory section, 9...
...High-speed buffer memory storage unit, 10...Control unit, FA, FB...Control flag, EA, EB...
Enable signal, UA, UB... In-use display signal, LA, LB... Field instruction signal, Pl, P2,
P3...Program, SP...System program.

Claims (1)

[Claims] 1. In a control method for a high-speed buffer memory of an information processing device that has a built-in high-speed buffer memory and is configured to temporarily transfer the contents of the main memory to the high-speed buffer memory for use, two sets of the high-speed buffer memories are used. and below a control flag indicating the operating state of the high-speed buffer memory,
The information of the program whose execution line will be assigned to the information processing device next is transferred from the main memory to a high-speed buffer memory that is not currently being used by the information processing device, and when control is passed to the program, the high-speed buffer memory is transferred. A high-speed buffer memory control method characterized by controlling the use of the buffer memory.