JPS6046540B2 - Electronic device manufacturing method - Google Patents

Abstract

PURPOSE:To obtain a highly reliable device without problems like disconnection and to increase the productivity by a method wherein a resin is filled and moulded after having inserted an electronic component in a mould of circuit substrate. CONSTITUTION:With the external outlet electrode looking downward, a semiconductor chip 2 is placed on a lower mould 11 which is provided with locating pins 10, the chip 2 being surrounded by the pins 10, on which an upper mould 12 is covered and then clamped. A resin A is filled through an inlet 13, which is formed on the upper mould 12, to form a buffer layer over the surface and side face of a chip 2. Then, the upper mould 12 is removed and the resin A solidified in the shape of the inlet 13 is removed. After that, another upper mould 15 is clamped similarly and a resin B is filled through this inlet 16 to make a circuit substrate 17 by surrounding a layer 14. Then, the upper mould 15 is removed to free the substrate 17 from the lower mould 11. After having removed the resin B remained in the shape of the inlet 16, the substrate 17 is turned around to match with the electrodes exposed herein resulting in the printing and formation of a wiring pattern 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which electronic components are simultaneously embedded during molding of a circuit board for electronic components, thereby improving productivity.

Conventionally, electronic components, mainly semiconductor chips, have been embedded in a circuit board made of an insulating material, and the surface of the semiconductor chip and the surface of the circuit board have been made approximately the same height, and then wiring has been installed to include the electrodes of the semiconductor chip. When forming a pattern, a method as shown in FIG. 1 has been proposed.

That is, in FIG. 1, an appropriate amount of resin such as FEP is put into the embedded part 3 of the semiconductor chip 2 provided on the circuit board 1, and the semiconductor chip 2 is put in and pressed with a flat plate to remove the resin. The buffer layer 4 is formed by molding.

After that, a wiring pattern (not shown) is formed to complete the electronic device. In this case, due to the shape error of the buried portion 3 and the shape error of the semiconductor chip 2, a gap is created between the semiconductor chip 2 and the buried portion 3 in the buffer layer 4, making it impossible to form thin film wiring using the commonly used vapor deposition method. It works to prevent things from happening. As it is clear from the fact that it has such a function, the buffer layer 4 is able to protect the surface 5 of the semiconductor chip 2 and the surface 7 of the circuit board 1.
It must have a surface 6 of approximately the same height as. For this purpose, the shapes of the embedded part 3 and the semiconductor/chip 2 must be made with high precision, and the quantitative supply of resin such as FEP also requires extremely high precision. It is very difficult to keep each height at a constant level. Therefore, mass production using such a method is difficult, and mass production leads to a decrease in yield and an increase in manufacturing man-hours. As a means to improve the above problem, it has been proposed to put a large amount of resin such as FEP into the embedded part 3 and to remove the resin that protrudes from the semiconductor chip 2 by mechanical or chemical polishing. In this case, it is not necessary to have a highly precise shape, etc., but on the other hand, polishing requires a sophisticated technique and at least damage to the semiconductor chip must be avoided. Techniques that meet these requirements require a higher level of technology than the aforementioned embedding with improved shape accuracy, and require a large number of production steps. The present invention is intended to eliminate such drawbacks, and by placing semiconductor chips in advance into a circuit board mold, filling the mold with other resin, and molding the circuit board, it is possible to reduce production man-hours and reduce wire breakage. This eliminates the drop in reliability.

An embodiment of a manufacturing method in which the present invention is applied to a circuit block of an electronic timepiece will be described with reference to FIGS. 2 and 3.

In FIGS. 2 and 3, a semiconductor chip 2 similar to that described in the conventional method is placed on the flat upper surface of a lower mold 11 having positioning pins 10, with the surfaces of external electrodes (not shown) facing downward. Place it in close contact with the

In this state, the semiconductor chip 2 is positioned with respect to the lower mold 11 (FIG. 2a). Next, the upper mold 12 is covered and tightened so that gaps 14a are formed on the upper surface and each side surface of the chip 2, and the resin A is filled through the injection port 13, and the buffer layer 1
4 (Figure 2b). After that, the upper mold 12 is opened, and the unnecessary part, that is, the solidified resin is removed from the injection port 13. Then, the upper mold 15 is covered in the same manner as the upper mold 12, and the upper surface and each side surface of the buffer layer 14 are covered with voids 17a. The lower surface of the upper mold 15 is tightly pressed against the lower surface of the lower mold 11 so that the upper mold 15 is formed, and the resin B is filled through the injection port 16 of the upper mold 15 to form the circuit board 17. (Figure 2c). Next, the upper mold 15 is opened, the circuit board 17 is taken out from the lower mold 11, and the solidified portion in the injection port 16 is removed (FIG. 2d). 20 is a gap created by the positioning pin 10.

Thereafter, the semiconductor chip 2 including external lead-out electrodes (not shown) is removed. The wiring pattern 18 is formed by printing conductive paste using a screen printing method. As a result, a circuit block 19 consisting of the semiconductor chip 2, the buffer layer 1 circuit board 17, and the wiring pattern 18 is completed (FIG. 2e). As is clear from the above explanation, since the semiconductor chip 2 is injected with the resins A and B into the lower mold 11 with the surfaces in close contact with each other, the surfaces of the semiconductor chip 2, the buffer layer 14, and the circuit board 17 are It is possible to suppress the height difference to 4 to 5 μm or less without using advanced technology.

This not only improves the manufacturing yield, but also eliminates disconnections at the difference portions of the wiring pattern 18, improving reliability.
In the description of the present invention, independent lower mold 11, upper mold A
Buffer layer 1 is formed by three independent molds including upper mold Bl2 and
Although a single circuit board 17 is formed, if the number of buffer layers 14 is to be further increased, four molds will be required, and these can be variously selected depending on the shape of the circuit block 19.

Of course, the above-described types and operations may be mechanically combined and mechanized. In this case, it is considered to be similar to ordinary injection molding, and the number of man-hours required for manufacturing is reduced, etc.
Needless to say, it is a manufacturing method that is easy to mechanize and automate. In the description of the present invention, resins A and B are used to form the buffer layer 14 and the circuit board 17, respectively. It can be anything as long as it does.

The present invention has been explained with reference to an example in which it is applied to a circuit block of an electronic watch, but it can also be applied to calculators, cameras, radios, etc.
The same applies to any device that uses electronic components.

Also, due to the circuit configuration, there is not only one semiconductor chip 2,
It is possible to embed multiple pieces at the same time, and it is also possible to embed other electronic parts such as resistors and capacitors in combination. In the description of the present invention, two L-shaped positioning pins 10 are used, but a plurality of round pins 21 may be used as shown in FIG. Various configurations are possible. It is also possible to eliminate the use of pins by employing positioning using vacuum or the like. Furthermore, if shape accuracy is not required, the semiconductor chip 2 is fixed to the lower mold 22 with its external electrode extraction portion (not shown) facing downward, as shown in FIG. may be formed. In the description of the present invention, the wiring pattern was formed by screen printing a conductive paste, but it may also be formed by a photographic method after forming a metal film on the entire surface by vacuum evaporation.

As described above, the present invention eliminates the reduction in reliability due to wire breakage by filling the mold with resin after electronic components are placed in the mold for the circuit board.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to a conventional method, FIG. 2 is a process diagram showing an example of the process of the present invention, FIG. 3 is a plan view of a lower mold, and FIG. A plan view showing an example,
FIG. 5 is a sectional view showing another manufacturing method. 2... Semiconductor chip, 11... Lower mold,
12...Top mold All4...Buffer layer, 15...
...Upper Bll7...Circuit board, 18...
・Wiring pattern, 19...Circuit block.

Claims (1)

[Scope of Claims] 1. A method for manufacturing an electronic device, characterized by comprising the following steps. (1) A first step of closely mounting the electronic component 2 on the flat upper surface of the lower mold 11 with the surface having the external electrode facing downward. (2) The upper mold 12 covers the electronic component 2 so that gaps 14a are provided on the upper surface and each side surface of the electronic component 2, and the lower surface of the upper mold 12 is placed closely on the upper surface of the lower mold 11, and the A second step of filling the gap 14a with the buffer insulating material 14 through the injection port 13 of the upper mold 12. (3) A third step of removing the upper mold 12 and removing the insulating material 14 solidified in the injection port 13. (4) The upper mold 15 is covered so that gaps 17a are provided on the upper surface and each side surface of the insulating material 14, the lower surface of the upper mold 15 is placed closely on the upper surface of the lower mold 11, and the upper mold 15 is The fourth step is to fill the circuit board insulating material 17 through the injection port 16.
process. (5) A fifth step of removing the lower mold 11 from the electronic device obtained in the fourth step. (6) Wiring pattern 1 on the external electrode of the electronic component 2
The sixth step is to connect and form 8.