JPS6046570B2 - integrated latch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a latch circuit, and in particular, when configuring a group of N latch circuits that share an output pin and an input pin, when an input is applied, a reset pulse (once) is applied to the entire latch circuit. The present invention relates to an integrated latch circuit that can set only the latch circuit to which input is applied after reset.

Most of the channel selection latch circuits used in conventional TVs, etc. are semiconductor integrated circuits, and it is possible to switch from the Nith latch circuit to the Ni+1th latch circuit using a group of latch circuits that share these output pins and input pins. At this time, reset all latch circuits once (remove the latch circuits while input is being applied).

), it was difficult to secure a circuit operation margin, and a bias circuit for the input switch was required. These are explained below.

First, a conventional circuit will be explained using FIG. In FIG. 1, 1, 2, 3, and 4 are transistors Ql, Q2, Q3 and a resistor Rl that constitute a first latch circuit, and 5 and 6 are a transistor Q4 and a resistor R2 that constitute an input circuit section.
, 7, 8 are four latch circuit groups consisting of the resistor R3 and transistors Q5, 9, 1O, 11, 12, which are the same circuits as the first latch circuit, and 13 is the bias circuit for the latch circuit. constant current source for giving 14,1
5, 16, 17 are four sets of input/output circuits configured to combine an input circuit and an output circuit so that the output can be shared by positive feedback to the input; 18, 19 are the terminals of constant voltage power supply B and the ground terminal;
20, 21, 22, and 23 are four terminal groups with common input and output, 24, 25, 26, and 27 are four input/output switch groups, and 28, 29, 30, and 31 are four load resistance groups. , 32
is a constant voltage power supply B, 33, 34 is a constant voltage power supply B'' for supplying bias to the input circuit and its internal resistance R8, 35
is an integrated latch circuit.

Next, the operation of the circuit shown in FIG. 1 will be explained.

In FIG. 1, after applying the constant voltage power supply B32, the four sets of latch circuits 9, 10, 11, 12 are off while no input is applied, and then when the first input switch 24 is turned on for a short time, During that time, the input current 111 flowing out from the base terminal of the input transistor Q45 is (however, 13E4 is the base-emitter forward voltage of the transistor Q4, B, B
'' are the voltages of the power supplies 32 and 33, respectively, and R2 and R8 are the resistance values of the resistors 6 and 34, respectively.

), and the second constant voltage power supply B''33 and R834 are selected at a level that saturates the transistor Q45,
Its collector potential ■Q4''.B (however, transistor Q4
Collector●Emitter saturation voltage■. It is assumed that ES4<B. ), resulting in 4 pairs. The potential of the emitter terminal of the transistor Q33, which is the common terminal of the latch circuit, is (However, ■8E3 is the base-emitter forward voltage of the transistor Q3.), and (■). . MON rises (2
) On the way to increasing towards the value of the expression, ■. 0MIN〉■
At the point BE, the first latch circuit 9 changes from OFF to ON and is held, and the base of the transistor Q58 is applied (where .beta.BE5 is the base-emitter forward voltage of the transistor Q5.

) flows and the output transistor Q58 is turned on, so that the potential at the terminal 20 becomes O [■], which is positively fed back to the transistor Q45. When the potential of the terminal 20 becomes 0CV], the input current l current L″1 flowing out from the base terminal of the input transistor Q45 becomes
R26 is selected so that R26 is not saturated, and its collector potential is, so four sets of latch circuits 9, 10, 1
The voltage at the emitter terminal of transistor Q33, which is the common terminal of transistors 1 and 12, is
−−view υ′ and becomes stable.

Next, remove the input applied to the first input switch 24,
When the entire system is in an unmanned state, the emitter terminal voltage of Q33 becomes such that only the run V circuit 9 of the Y voltage 1 remains on.

Next, when the second input switch 25 is turned on for a short period of time, the second latch circuit 10 operates in exactly the same way as the first latch circuit group 9, and the potential of the common terminal of the latch circuits is as described in (2) above. ■ As shown in Eq.

Since 0M1N=B-■BE, the first latch circuit 9
The voltage between the base and emitter of the transistor Q33 disappears and is cut off, and the first latch circuit 9 is reset.

At the same time, the second latch circuit 10 is set and turned on, and even after the input applied to the second input switch 25 is disconnected and turned off, only the second latch circuit 10 is turned on, and the other latch circuit groups 9 and 11 are turned on. , 12 are turned off. As explained above, it is possible to turn on only the latch circuit to which an arbitrary input is applied and turn off the other latch circuits, but the key point of this operation is the condition for resetting the other latch circuits. 5) It is necessary to select the value of the resistor R26 to satisfy the equation, but since the value of the current amplification factor of the transistor Q45 is related, in order to actually satisfy the relationship of the equation (5), the transistor Q45 must be selected carefully. It becomes necessary,
It is difficult to construct an integrated latch circuit using semiconductors. Further, the need for an external second constant current power supply B''33 has the disadvantage of increasing the number of peripheral circuits.In order to achieve this purpose, the integrated latch circuit of the present invention , each of which is provided in each of the plurality of input/output circuits, whose base is connected to a switch that selects a latch circuit, and whose collector is connected to the transistor of the latch circuit, the transistor of the other input/output circuit, and the base of the above-mentioned output circuit. When the input signal is applied to the multi-collector transistor for positive feedback to the input and for detecting the input signal, and the other latch circuit, and the one latch circuit is inverted from the on state to the off state, the above one The latch circuit and the other latch circuit are both configured to have a period of time in which they are in an on state, and the circuit detects the sum of the input currents of the latch circuit based on the collector output current of the multi-transistor. a detection circuit that detects that both the latch circuit and the other latch circuit are turned on;
A pulse generating circuit is provided which generates a reset pulse signal in response to the signal from the detection circuit, and after resetting all the latch circuits included in the latch circuit group in response to the reset pulse signal, the other one of the latch circuits is reset. This allows only the circuit to be reset.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
FIG. 2 is a circuit diagram showing one embodiment of an integrated latch circuit according to the present invention.

In FIG. 2, parts with the same symbols as in FIG.
6 and 37 are 211n current detection circuits 37, 38, and 39 are resistor R8 and transistor Q7 that constitute a pulse generation circuit 40 for transmitting the output of the 211n detection circuit to the next stage.

FIG. 3 is an explanatory diagram of the operation of FIG. 2, where the horizontal axis is time t,
Stl, st2, st3, st4 on the vertical axis indicate input switches 24, 2 to input/output terminals 20, 21, 22, 23, respectively.
5, 26, and 27 are on, and Ic
．． e, is the current applied to the 211rL8 output circuit 37, VR
are the voltages applied to the common terminals of the four latch circuit groups, and VOl, ■02, V03, and ■04 are the output voltages generated at the input/output terminals 20, 21, 22, and 23, respectively.

Next, the operation of the embodiment shown in FIG. 2 will be explained with reference to FIG. 3, which is a time chart for explaining the operation.

First, after turning on the power supply B32, all the latch circuit groups 9, 10, 11,
12 is off, the output voltage ■01, ■02, V0
3, ■04 are all Hjgll and B [■], and Tokifu,
When the switch 24 is turned on at the timing of Stl, the input current 111'' is (however, VBE6 is the transistor Q6
36 base-emitter forward voltage.

) flows, and since transistor Q636 is a multi-collector transistor with three collectors (the areas of the three collectors are equal), the current flows from the two collectors toward the load (excluding the collector connected to the base of Q6). ) Each collector current is equal to equation (8), and the values of Rl, R2, and B are selected so as to satisfy equation (9) above, so the first latch circuit 9 changes from off to on and is held. , the terminal 20 is similar to the explanation of the circuit in FIG.
■ Output voltage.

1 becomes 0 [■], and the emitter common terminal voltage VCOM changes from 0CV to B-2VBE and stabilizes, and also goes to the 211n detection circuit 37, and the remaining collector current ID, . t=Iil'''' flows in, but its output is off and remains ■Det=B [■]).

Next, at time T2, when the switch 25 is turned on at the timing St2, the second latch circuit 10 operates in exactly the same way as the first latch circuit 9, so the multi-collector transistor of the second latch circuit section 10 A current equivalent to equation (8) flows out from the end of CO2, and the time T
During the reversal time from when the first latch circuit 9 is turned on to when it is turned off, a current of approximately 2111
The current flows into the sequential output circuit 37, the 211n detection circuit 37 is turned on, the voltage becomes 0 [V], and the transistor Q739 is turned on (IB7=B−V average, /R6), where a base current flows.
) Since its collector is connected to the emitter common terminal, the emitter common terminal voltage VCOM rises from B-2VBE to B [■], and the first
, the second latch circuits 9 and 10 turn from on to off, but
Since the second input switch 25 remains on even after the first latch circuit 9 is turned off, the first latch circuit 9
is turned off, the second latch circuit 10 is turned on, and VO2
is maintained in a state where it changes from B [■] to O [■]. Similarly, in accordance with the timing at which the input switches 26 and 27 are applied at times T3 and t4, their outputs ■.

3, ■04, an output having a phase as shown in the waveform diagram of FIG. 3 is obtained.

In the above embodiments, the operation was explained using four sets of latch circuits as an example, but the same principle can be easily extended to any N sets of latch circuits.
For example, in applications such as channel switching for selecting electronic channels on consumer color TVs, many latch circuits are equipped with 8 to 1 latch circuits, and it is obvious that the present invention can be easily applied to these applications.

As is clear from the above description, according to the present invention, when setting an arbitrary latch circuit and transferring information to another latch circuit, two latch circuits are set for a moment without using complicated means. An integrated latch circuit with stable operation and simple peripheral circuitry can be realized by a simple circuit configuration that utilizes the fact that the 211n current is turned on simultaneously and uses the information that the 211n current flows as a stable reset signal. Therefore, the practical effect is extremely large.

Further, the integrated latch circuit according to the present invention is extremely effective in that it can be widely applied to function switching in consumer use, industrial use, industrial use, and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional latch circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. In the figure, 9, 10, 11, 12 are latch circuits, 14, 15
, 16 and 17 are input/output circuits, 37 is a detection circuit, and 40 is a pulse generation circuit.

Claims (1)

[Claims] 1 Consisting of a latch circuit group including a plurality of latch circuits and an input/output circuit group including a plurality of input/output circuits each connected to the latch circuit, only one latch circuit arbitrarily selected from the latch circuit group. After setting, when an input signal is applied to another latch circuit, only that other latch circuit is set, and all the remaining latch circuits including the one latch circuit are reset. In an integrated latch circuit that shares an input signal line and an output signal line of an input/output circuit, each of the plurality of input/output circuits is provided with a base connected to a switch for selecting the latch circuit, and each collector is connected to a switch for selecting the latch circuit. A transistor of the latch circuit, a transistor of another input/output circuit, a multi-collector transistor connected to the base, respectively, for positive feedback of the output to the input and for detecting an input signal, and an input signal to the other latch circuit. When the one latch circuit is reversed from the on state to the off state by applying a a detection circuit comprising a circuit that detects the sum of the input currents of the latch circuit based on the collector output current of the transistor, and detects when the one latch circuit and the other latch circuit are both turned on; a pulse generating circuit that receives the signal and generates a reset pulse signal, and after resetting all the latch circuits included in the latch circuit group in response to the reset pulse signal, only the other latch circuit is reset. An integrated latch circuit characterized by being resettable.