JPS6046915B2 - Data extraction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data sampling method, and in particular provides a data sampling method that is optimal for a television multiplex teletext receiver having a function of automating the sampling of multiplexed signals.

First, the present invention will be explained with reference to an example in which the present invention is used in this television multiplex teletext receiver.

BACKGROUND ART In recent years, technology related to multiplex television broadcasting has developed, and various television multiplexing systems have been proposed.

In television multiplex teletext broadcasting, which has been proposed as one of these methods, character information is composed of binary signals for one horizontal scanning period, and a predetermined binary signal is composed as a synchronization signal for data and evening processing of this information. The Fleming code is superimposed on one specific line of the vertical blanking period of the television signal, for example, the second line and the 28th line (hereinafter referred to as 20H and 283H, respectively). The receiver that receives this data slices it, extracts it, digitally processes it, and displays the character information on a cathode ray tube. At this time, the data waveform is often degraded due to ghosts, phase distortion and noise due to the IF characteristics of the receiver. Therefore,
In order to sample data well in this type of receiver, it is necessary to always set the data slice level to the optimum position. Conventionally, the slice level has often been manually adjusted using a variable resistor or the like, but this requires readjustment because the data level fluctuates. The present invention automatically ensures an optimal slice level even if the data level fluctuates. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a multiplex teletext receiver according to an embodiment of the present invention, in which 1 is a buffer amplifier that amplifies a video signal to an appropriate level, and 2 is a buffer amplifier that extracts DATA from the video signal. The data sampling circuit 3 of the present invention oscillates in synchronization with the phase of DATA during the multiplex period, and oscillates in synchronization with the horizontal AFC pulse of the television receiver during other periods, thereby making bits synchronized with the pulse signal of DATA. This is a clock generation circuit that generates a clock pulse (BITCK). 4 are horizontal and vertical synchronizing signals HSYNC, . Synchronous separation circuit that separates VSYNC, 5
6 is a horizontal position counter that operates as input of the bit clock pulse BITCKl horizontal AF'C pulse and performs horizontal signal processing; 6 is a vertical position counter that operates with HSYNC and VSYNC as input and performs vertical signal processing; 7 is D. Processing of the control code included in the ADT For example, the transmitted program code is compared with the program selected on the keyboard 11 of the receiver, and if the two match, the control code is used to put the memory 10 into a writing state. - This is a signal processing circuit.

8 is an X address counter that specifies the horizontal address of the memory, 9 is a Y address counter that specifies the vertical address, and 12 is a TV signal and M
It has the function of displaying it as an IX or displaying it alone!
This is a power switching circuit.

FIG. 2 shows a block diagram of an embodiment of the data extracting circuit 2 of the present invention, FIG. 3 shows an explanatory diagram of data slicing, and FIG. 4 shows a waveform diagram for explaining the data extracting circuit.

In FIG. 2, 13 is an oscillator for creating clock pulses used for data sampling processing, 14 is a reversible counter that counts these clock pulses, 15 is a first DA converter circuit that converts the digital output of 14 into an analog value, 16 and 17 are a first register and a second register that latch the output of the counter 14, respectively; 18 and 19 are second DA conversion circuits that convert the outputs of the first register 16 and second register 17 into analog values, respectively. and a third DA conversion circuit.

20 and 21 are a first comparator and a second comparator that slice and extract DADT from the video signal; the slice level of the comparator 20 is the output level of the first D-A conversion circuit 15; The slice level is an intermediate value between the output levels of the first and second saturation-A conversion circuits 18 and 19.

22 is a data gate circuit that outputs DATA only during the period of 20H1283H.

Reference numeral 24 denotes a fleming code detection circuit which decodes a fleming code composed of seven predetermined binary signals from the video signal inputted through the first comparator 20 and outputs a fleming code detection pulse as shown in FIG. 4c. It is.

Further, 23 is composed of, for example, a mono multivibrator, etc., and generates one pulse for each multiplex line of 20H and 283H, in which the information already mentioned and the Fleming L code are multiplexed, and as shown in FIG. 4b. This is a sampling pulse generation circuit which outputs a sampling pulse as shown in FIG. 4d, which is obtained by appropriately delaying the rising edge of the multiplexed line to a position that coincides with the fleming code detection pulse outputted from 24. 25 is a flip-flop whose Q terminal output rises while Fleming code detection is being performed; the output of the Fleming code detection circuit 24 is input to the D terminal, and the sampling pulse obtained from the sampling pulse generation circuit 23 is input to the clock terminal CK. is input to.

26 and 27 output signals indicating the rise of the Q terminal output and the rise of the n terminal output (fall of the Q terminal output) of the flip-flop 25, respectively. an AND gate and a second AND gate.

28 is an initial reset circuit that generates a pulse of positive polarity (initial reset pulse) when the power supply of the receiver becomes ON state, inputs this to the reversible counter 14 as a reset signal, and also outputs it via the 0R gate 29. and set 14 to ] state.

The circuit configuration has been described above, and the specific operation will be explained below.

In FIG. 2, the terminal 30 has a 20/2831 signal as shown in FIG. 4b output from the vertical position counter 6 in FIG.
1 signal is input.

Further, a video signal output from the buffer amplifier 1 shown in FIG. 1 is input to the terminal 31. In FIG. 2, the reversible counter 14 is reset to a count of '6 zero' and 2 by an initial reset pulse generated by the initial reset circuit 28 when the power supply of the receiver becomes ON state, and at the same time becomes in the UP mode and is generated by the oscillator 13. Count up the clock. This count value is converted into an analog value by the first DA conversion circuit 15, which becomes the slice level of the first comparator 20. As the count value of the reversible counter 14 increases, the slice level increases and when it reaches the lower limit V2 of the slice level shown in FIG. Pulse creation circuit 23
The output of the Q terminal of the flip-flop rises as shown in FIG. 4e by the sampling pulse shown in FIG. 4d obtained from this. As a result, the output of the first AND gate 26 has the fourth
A slice level lower limit detection signal as shown in FIG. The value of slice level V2 of is output. The counter 14 further increases the count number and raises the slice level of the first comparator 20, and when it reaches the slice level upper limit V1 as shown in FIG. Detection pulses no longer occur. As a result, the Q terminal output of the flip-flop 25 falls, and the second gate 27 outputs a slice level upper limit detection signal as shown in FIG. 4g. As a result, the count number at this time is latched in the second register 17, and the upper limit slice level 1 is outputted to the third DA conversion circuit 19. The second comparator 21 is configured to receive an intermediate level between the outputs 18 and 19, and after the upper limit slice level 1 is detected, the slice level V is intermediate between the upper limit and the lower limit. will be input. The slice level upper limit detection signal output from the second AND gate 27 switches the reversible counter 14 from UP mode to DOWN mode, and after detecting the upper limit slice level, the reversible counter 14 counts down in the opposite manner to the above operation. I'll go. As the count value decreases, the slice level of the first comparator 20 decreases, and when it reaches the slice level lower limit V2 shown in FIG. 3, the slice level lower limit detection signal is output from the first AND gate 26 as described above. This is 0R gate 29
is input to the reversible counter 14 via the reversible counter 1
4 enters the UP mode, increases the count again, and repeats the above operation. As described above, according to the present invention, an optimal slice level is always ensured even if the data level changes. Although the automation of data extraction has been described above with reference to an example of a multiplex teletext receiver, the present invention is not limited to this and can be applied to other data transmission systems.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the configuration of a multiplex teletext receiver according to an embodiment of the present invention, FIG. 2 is a block circuit diagram of main circuits according to an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining data slicing operation. , FIG. 4 is an explanatory waveform diagram of the data extraction circuit 2. In FIG. 1...Buffer amplifier, 2...Data extraction circuit, 3...Clock generation circuit, 4...
... Synchronization separation circuit, 5 ... Horizontal position counter, 6 ... Vertical position counter, 7 ... Control signal processing circuit, 8 ... X address Counter, 9... Y address counter, 10...
...Memory, 11...Keyboard, 12.
・Output switching circuit, 13...Oscillator, 14...
...Counter, 15...First D-A converter,
16...First register, 17...Second register, 18...Second D-A converter, 19...
Third DA converter, 20...First comparator, 2
1...Second comparator, 22...Data gate, 23...Sampling pulse generation circuit, 2
4... Fleming code detection circuit, 25...
・Flip-flop, 26... 1st AND gate, 27... 2nd AND gate, 28...
Initial reset circuit, 29...0R gate, 30
...20/28 target signal input terminal, 31...video signal input terminal.

Claims (1)

[Claims] 1. After the power is turned on, a clock signal with a constant period that constantly oscillates is counted forward, and this counted value is converted one by one into an analog value, and this information is transmitted simultaneously as a synchronization signal for data processing. The binary signal is sliced one by one at the slice level having the analog value, and when the slice level that rises one by one from the reference level as the forward count detects this binary signal, a lower limit detection pulse is set, and the slice level is further increased. When the slice level to be detected no longer detects this binary signal, an upper limit detection pulse is raised, and the count value when this lower limit detection pulse is raised is latched and converted into an analog value as the lower limit slice level. , latching the count value when the upper limit detection pulse rises and converting it into an analog value as an upper limit slice level, slicing the information at a slice level having an analog value intermediate between these two analog values, and After the upper limit detection pulse rises until the lower limit detection pulse rises, the forward counting of the clock signal is switched to backward counting, and then when the lower limit detection pulse rises again, the clock signal The data extraction method is characterized in that the backward count is switched back to the forward count, and the latched upper and lower limit count values are constantly corrected according to the upper and lower limit levels of the transmitted information. 2. Information consisting of a binary signal and data consisting of a fleming code consisting of a predetermined binary signal as a synchronization signal for data processing of this information are superimposed on one specific line of the vertical blanking period of the television signal. Claim 1 is characterized in that the Fleming code is a binary signal that is sliced and detected.
Data extraction method described in section.