JPS626396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data extraction circuit, and provides a data extraction circuit that is particularly suitable for use in environments where the phase, amplitude, etc. of data are likely to become unstable during transmission. It is something to do.

Hereinafter, an example of a television teletext receiver will be described as an example to which the present invention is applied.

In recent years, technology related to multiplex television broadcasting has developed,
Along with this, various television multiplexing systems have been proposed. In television teletext broadcasting, which has been proposed as one of these methods, character information is composed of binary signals for one horizontal scanning period, and a predetermined binary signal is composed of a synchronization signal for data processing of this information. Fleming code and the vertical blanking period of a television signal for a particular line, for example, the 20th line and the 28th line (hereinafter this will be referred to as each
20H and 283H) and transmit them sequentially.
Therefore, the receiver that receives this data slices it, extracts it, digitally processes it, and displays the character information on a cathode ray tube. At this time, the data waveform often deteriorates due to ghosts, phase distortion and noise due to the IF characteristics of the receiver. As a result, in order to sample data well in this type of receiver, it is necessary to always set the data slice level to the optimum position.

Conventionally, the slice level has often been manually adjusted using a variable resistor or the like, but this requires readjustment every time the data level changes. The present invention automatically ensures an optimal slice level even if the data level fluctuates.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a block diagram of a teletext receiver according to an embodiment of the present invention, in which 1 is a buffer amplifier that amplifies the video signal to an appropriate level, and 2 is a data extractor that extracts DATA from the video signal. It is a circuit. 3 generates a bit clock pulse (BITCK) synchronized with the DATA pulse signal by oscillating in synchronization with the phase of DATA during the multiplex period, and oscillating in synchronization with the horizontal AFC pulse of the television receiver during other periods. This is a clock generation circuit. 4 is a synchronization separation circuit that separates horizontal and vertical synchronization signals HSYNC and VSYNC from the video signal;
5 is a horizontal position counter that operates with bit clock pulse BITCK and horizontal AFC pulse as input and performs horizontal signal processing; 6 is HSYNC and VSYNC
7 is a vertical position counter that operates with input as input and performs vertical signal processing. 7 processes the control code included in DATA, for example, compares the transmitted program code with the program selected on the keyboard 11 of the receiver, and This is a control signal processing circuit that puts the memory 10 in which a match is found into a write state. 8 is an X address counter that specifies the horizontal address of the memory; 9 is a Y address counter that specifies the vertical address; 12
is an output switching circuit that has the function of mixing the memory output signal with the television signal or displaying it alone. Next, an embodiment of a data extraction circuit to which the present invention is applied will be described with reference to FIG. In addition, FIG. 3 is a waveform diagram for explaining the operation of FIG.
FIG. 4 is a waveform diagram for explaining the operation of extracting transmitted data.

First, the circuit configuration will be described according to FIG. 2. The circuit of this embodiment can be roughly divided into the first
The circuit system and the second circuit system for the lower limit detection pulse are arranged in a similar configuration. Therefore, when explaining the circuit configuration, circuit blocks that perform the same circuit operation will be given the same number, and one explanation will be given with a, and the other explanation will be given with b. Omitted.

In FIG. 2, 20a is the first switching circuit according to the present invention, which is a flip-flop (hereinafter referred to as
It's called FF. ) 21a, and two first and second AND circuits 22a and 23a. FF
21a is switched to the set state by an upper limit detection pulse to be described later, and reset pulse generation circuit 1
It is switched to the reset state by the reset pulse given from 6.

The reset pulse generating circuit 16 is controlled by the timer circuit 15 so as to generate one pulse signal (negative polarity) after a predetermined period of time (to be described later) has elapsed starting from the vertical synchronizing signal. Further, the first AND circuit 22a obtains the AND of the output Q of the FF 21a and the vertical pulse. Furthermore, the second AND circuit 23a
obtains the AND of the output of the FF 21a and the vertical pulse. The first reversible counter 24a performs forward counting (up counting) using the pulses output from the first AND circuit 22a, and backward counting (down counting) using the pulses output from the second AND circuit 23a. . It should be noted that the first reversible counter 24a has a count of MAX when the power is turned on,
That is, it is assumed that it is preset to the maximum counting state.

The first digital-to-analog converter (hereinafter referred to as a D/A converter) 25a converts the output signal (digital) of the first reversible counter 24a into an analog signal. Note that when the first reversible counter 24a performs forward counting, the voltage level of the output signal of the first D/A converter 25a increases according to this count value; When performing this, the voltage level decreases according to the count value.

26 is an upper limit detection circuit according to the present invention, which includes a slicer 27a and a Fleming code detection circuit 28a.
It is composed of. First slicer 27a
slices the upper limit of the video signal input from the terminal 200 based on the voltage level output from the first D/A converter 25a. This first slicer 27a is constituted by a comparison circuit using a well-known operational amplifier or the like. The fleming code detection circuit 28a outputs a fleming code detection pulse when a preset fleming code matches a predetermined binary code detected by the first slicer 27a from the transmitted video signal. Further, the above-mentioned voltage signal outputted from the first D/A converter 25a is supplied to one input terminal of the third slicer 30 via a resistor Ra. Note that the resistance values of the resistors Ra and Rb are made the same.

As mentioned above, 20a, 24a, 25a, 27
The first circuit system constituted by a and 28a determines the upper limit detection level of the transmitted video signal applied to the terminal 200. Also, 2
0b, 24b, 25b, 26b, 27b, 28b
The second circuit system constructed by the above operates in exactly the same manner as the first circuit system, except that the second reversible counter 24b is preset to count zero when the power is turned on. Therefore, this second circuit system determines the lower limit detection level of the video signal applied to terminal 200. As a result, the potential at the connection point A between the resistors Ra and Rb, which have the same resistance value, is
This is the intermediate value between both voltage levels output from the 2D/A converters 25a and 25b. Therefore, the third slicer 30 slices the video signal applied to the terminal 200 using this intermediate value as a reference voltage.

By the way, the terminal 200 is provided with a video signal as shown in FIG. 3A, which is obtained by receiving a broadcast signal transmitted through the air. In the video signal of FIG. 3A, 31 indicates a vertical synchronizing signal, and 32 indicates a character signal. The vertical synchronizing signal 31 is separated from the video signal by a circuit not shown.
The vertical pulse 33 shown in FIG.
b, 23a, 23b is supplied to one input terminal b. Further, this vertical synchronization signal 31 is also given to a timer circuit 15, and this circuit 15 receives a character signal 32.
In order to control the reset pulse generating circuit 16 so that the reset pulse is generated at an appropriate time before the position where the vertical pulse 33 is multiplexed, timing is started from the time when the vertical pulse 33 is applied. At this point, each output Q of the first and second FFs 21a and 21b is at "L" level, and each output is at "H" level. Therefore, the second and third AND circuits 23a and 23b output the vertical pulse 33 applied to each input terminal b. This vertical pulse 33 is transmitted to the first reversible counter 24a.
and the up input of the second reversible counter 24b. Since the first reversible counter 24a is preset to count MAX when the power is turned on, it performs backward counting every time the vertical pulse 33 is supplied. When backward counting is performed, the output signal of the first reversible counter 24a, in other words, the count value gradually decreases each time the vertical pulse 33 is supplied, and the output signal of the first reversible counter 24a gradually decreases each time the vertical pulse 33 is supplied.
The voltage level of the voltage signal 5a also gradually decreases in accordance with the above-mentioned count value.

The voltage signal is supplied to the input terminal a of the first slicer 27a and the input terminal a of the third slicer 30 via the resistor Ra. The first slicer 27a slices the video signal as shown in FIG. 4 supplied to the terminal 200 with reference to the voltage signal each time the vertical pulse 33 is supplied. Therefore, at first, since the level of the voltage signal given from the first D/A converter 25a is higher than _V1 in FIG. Fleming codes that are created are not detected. the result,
Since the Fleming code detection circuit 28a cannot find a match with the code prepared in advance, the first FF
21a is not set. With this, 1FF21
Each output Q, of a is not inverted, and the first reversible counter 2
4a, the next vertical pulse 33 is applied as a backward counting pulse via the second AND circuit 23a as described above. Therefore, the first D/A converter 2
5a supplies the first slicer 27a with a voltage signal having a lower voltage level than the level of the previous voltage signal. In this way, the reference voltage of the first slicer 27a is lowered every vertical cycle, but eventually reaches _V1 or lower in FIG. 4, and the transmitted fleming code is detected from the video signal.

When the first slicer 27a drops to the reference voltage at which the Fleming code can be sliced at the upper limit of the video signal, the first Fleming code detection circuit 28a detects a match with a code prepared in advance and detects a third
A detection pulse 35 as shown in FIG. C is output. This detection pulse 35 is supplied to the set terminal of the first FF 21a, and at this point the first FF 21a is switched from the reset state to the set state. Therefore, the 1st FF
The output Q of 21a is inverted to an "H" level signal 36 as shown in FIG. 3D.

As a result, the gate of the first AND circuit 22a is opened and the gate of the second AND circuit 23a is closed. As a result, the vertical pulse 33 supplied to the terminal 100 passes through the first AND circuit 22a and is applied to the up input of the first reversible counter 24a.
The first reversible counter 24a reverses to forward counting, and the voltage signal applied to the first slicer 27a increases. Therefore, the first reversible counter 24a alternately inverts backward and forward counts depending on whether or not the first slicer 27a detects a framing code from the video signal. At this time, the level of the voltage signal applied to the first slicer 27a corresponds to the upper limit of the video signal.

On the other hand, the second circuit system operates completely opposite to the first circuit system, and the level of the voltage signal output from the second slicer 27a corresponds to the lower limit of the video signal, and the level of the voltage signal output from the second slicer 27a corresponds to the lower limit of the video signal. is alternately reversed to count forward and backward.

That is, while the first circuit system is operating as described above, the second reversible counter 24b performs forward counting by the vertical pulse 33 supplied from the second switching circuit 20b in the present invention. I do. As already mentioned, the second reversible counter 24b is preset to count zero when the power is turned on. Therefore, the voltage level of the voltage signal obtained from the second D/A converter 25b gradually increases every vertical period. The second slicer 27b slices the video signal supplied from the terminal 200 based on the level of the voltage signal supplied from the second D/A converter 25b. Therefore, the second slicer 27b
starts slicing the video signal at a voltage level lower than V ₂ in Figure 4, and increases this slicing level every vertical period until it exceeds the V ₁ level mentioned above, and then it is detected to the next stage. Output fleming code. As a result, the second fleming code detection circuit 28b outputs a detection pulse. This detection pulse is supplied to the set terminal of the second FF 21b, and at this point the second FF 21b is switched from the reset state to the set state. Therefore,
The output Q of the second FF 21b is inverted from the "L" level to the "H" level. As a result, the gate of the third AND circuit 22b is opened, and the gate of the fourth AND circuit 23 is opened.
b closes its gate. The subsequent operation is the same as that described for the first circuit system, and the second slicer 2
The level of the voltage signal applied to 7b corresponds to the lower limit of the video signal.

As described above, the operations of the first and second circuit systems are performed every vertical period, but when the first and second slicers 27a and 27b are supplied with the upper and lower limit reference voltages, respectively, the first and second slicers 27a and 27b are 2
The reversible counters 24a and 24b alternately repeat backward and forward counting every vertical cycle. As a result, the first and second slicers 27
The slice levels of a and 27b will vary, but this is due to the difference between the first and second D/A converters 25.
If the quantization of a and 25b is made dense and the voltage step of the count value "1" is reduced, it can be ignored in practice.

By repeating the circuit operations described above, the upper limit level V ₁ and lower limit level V ₂ as shown in FIG. 4 are determined. By the way, since the resistors Ra and Rb are set to the same value, the voltage level V ₀ at point A of the combining circuit 29 is an intermediate level between the upper limit level V ₁ and the lower limit level V ₂ . Therefore, even if the amplitude of the video signal changes as shown in FIG. 4 while the video signal is being transmitted, the voltage level V ₀ is always maintained at a voltage level approximately midway between the voltage levels V ₁ and V ₂ . Therefore, by slicing the video signal supplied to the terminal 100 using this voltage level as a reference, the character signal 32 formed of the transmitted binary digital data can be extracted accurately. The third slicer 30 works in this way. Note that the resistors Ra, which constitute the composite circuit 29,
Although Rb is a fixed resistance, a variable resistor may be used instead. As already mentioned, the upper limit V ₁ and the lower limit V ₂ are varied in accordance with fluctuations in the video signal, so the slice level of the third slicer 30 is always near the center of the video signal, allowing accurate extraction.

Furthermore, the data sampling circuit of the present invention is not limited to the above-mentioned teletext broadcasting receiver, but can also be applied to other data transmission systems.

As described above, the present invention includes a first signal processing path that automatically detects the upper limit level of an input signal, and a second signal processing path that automatically detects the lower limit level of the input signal, and An output signal with upper and lower limit voltage levels set is obtained from a combining circuit provided between the second signal processing path and the second signal processing path.

According to the data extraction circuit configured as described above, even if the level of the input signal fluctuates, the center level of the output signal is always maintained at a predetermined voltage level.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the circuit configuration of a teletext receiver suitable for applying the data sampling circuit of the present invention, FIG. 2 is a block circuit diagram showing an embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the circuit operation of the data extraction circuit of the present invention, and FIG. 4 is a waveform diagram showing the data extraction operation. 20a, 20b...first and second switching circuits,
24a, 24b...Reversible counter, 25a, 25b
...D/A converter, 26a, 26b...Upper limit and lower limit detection circuit, 29...Synthesizer circuit, 30...Slicer, _V1 ...Upper limit level, _V2 ...Lower limit level,
V ₀ ...center level.

Claims (1)

[Claims] 1. Data reception in a format in which digital data in which one unit is a synchronization pulse, a fleming code formed of a predetermined binary code, and digital information expressed in binary values is transmitted at a constant cycle. The device includes a reversible counter that starts counting backward from a maximum value when the synchronization pulse separated from received digital data is applied, and a voltage level is varied according to the count value of the reversible counter. a digital-analog converter that generates a first voltage signal; a first slicer that slices the received digital data using a first electrical signal of the digital-analog converter; a Fleming code detection circuit that outputs a detection pulse only when the code matches the Fleming code; and a Fleming code detection circuit that outputs a detection pulse only when the code matches the Fleming code; a first circuit system comprising a switching circuit for switching the counting mode from reverse to forward, and switching to the original backward counting mode when the detection pulse is not applied; Only the reversible counter is set to start counting forward from a zero value, so that the digital-to-analog converter outputs a second electrical signal.
A second circuit system having the same configuration as the circuit system is provided, and a third electrical signal having an intermediate voltage level of both signals is generated from the first electrical signal and the second electrical signal, and the third electrical signal is generated from the first electrical signal and the second electrical signal. A data extracting circuit comprising: a third slicer for slicing and extracting the data at the voltage level of the third electrical signal.