JPS6048708B2 - logical device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic device that facilitates the detection and diagnosis of failures occurring in various logic circuits in information processing devices, digital communication devices, and the like.

In recent years, the integration of ring-shaped circuits has progressed, and large-scale integrated circuits (hereinafter referred to as L
It is called SI. ) are being incorporated into information processing equipment, etc. Among these LSI failures, failures in bonding portions that connect circuit elements account for a large proportion.

This defect in the manufacturing of the bonding portion appears as, for example, poor contact in the bonding of the Li terminal. Conventionally, the method for diagnosing this failure is generally shown as υ.

That is, in this type of technique, results are predicted during a step in the system and operation, and errors are accounted for by differences resulting from a comparison between the actual value obtained during that step and the predicted value. It was intended to display information and to correct errors that occurred during system operation.

Such correction is accomplished by repeating the operation in which the error occurred, assuming that the error will not occur again. Another method involves injecting a correction amount into the results obtained during the step in which the error occurred to compensate for the error. Therefore, the prior art as described above cannot determine the actual cause of the error. That is,
It may not be possible to identify the structural failure corresponding to the erroneous operation. As a method for correcting such defects, in order to compare the comparison results with the faults that can be detected from the comparison results, we conducted a simulation of all the faults in the system through a large number of tests.

Next, a dictionary was prepared in advance in which a plurality of test results were comprehensively judged and the test results corresponded to failures, that is, the physical locations of failures. When an error occurs in the system during operation, these pre-prepared tests are given to the affected device, and based on the results, the physical location of the fault is obtained by referring to a dictionary. Next, repair is performed by replacing the physical circuit board containing this location with a board that has been previously confirmed to be normal. With such prior art, a huge amount of expense and a long development period were required for simulation. The object of the present invention is to
An object of the present invention is to provide a logic circuit that facilitates the detection of a failure in a bond portion of a device.

Another object of the present invention is to provide a printed circuit board on which an LSI is mounted;
The object of the present invention is to provide a logic circuit that can perform failure detection on a unit-by-unit basis. Another object of the present invention is to provide a logic device that allows a logic designer to detect faults simply by adding certain elements to the circuit that performs its original function. The configuration of the present invention is a logic device including a plurality of logic units to which a common control signal is input, and each of the plurality of logic units includes a first logic circuit that inputs and processes data; said first in response to a control signal.
a second logic circuit that outputs either the output signal of the first logic circuit or a predetermined output signal according to the output signal of the logic circuit; and a third logic circuit that performs a logical operation, and when the control signal is applied so that a predetermined output signal is output from each of the second logic circuits of the plurality of logic units, an arbitrary logic unit. When a predetermined output signal from one or more logic units predetermined as data input to the third logic circuit of is erroneously supplied, a logic value different from that when it is correctly supplied is outputted. This is a logical device characterized by the following.

In the present invention, by setting the logic states of the output lines of the logic circuit to the logic values "1" and "O" at two different timings, the logic states of the inputs of the logic circuit connected thereto are respectively set to the logic values "1" and "O". The principle is that fixed 1 faults and fixed 0 faults on the wiring can be detected by observing whether or not they correspond to the above.

3. The present invention is based on a principle that can be effectively and easily utilized for detecting and diagnosing failures in bond portions of large-scale integrated circuits in electronic data processing systems constituted by large-scale integrated circuits.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1A, there is shown a logical block configuration, which is a feature of the present invention, on a large-scale integrated circuit chip (hereinafter referred to as an LSI chip) to which the present invention is applied. The LSI chip 100 is electrically connected to other LSI chips etc. via a first input signal line 101, a second output signal line 108, a second input signal line 107, and a third output signal line 105. and logically connected. Among the functions that an electronic data processing system should originally have depending on the purpose of the system,
The functions to be performed by the SI are achieved by the first logic circuit 103 which receives the first input signal line 101 and outputs the first output signal line 102. Therefore, in FIG. 1A, the components other than the first signal line 101, the first output signal line 102, and the first logic circuit 103 are added to achieve the object of the present invention. The third logic circuit 104 receives the first input signal line 101 as an input, and determines whether the logic state of the input is all the logic value "O" or the logic value "1", or if it is something else. Check the third output signal line 1
05, a signal is output which makes the former correspond to the logical value "0.p" and the latter corresponds to the logical value "1". For example, an exclusive OR circuit
This applies. The second logic circuit 106 inputs the second input signal line 107 and the first output/output signal line 102, and outputs the logic of the second output signal line 108 according to the logical instruction of the second input signal line 107. The state can be controlled in the following three ways. One embodiment of the second logic circuit 106 is shown in FIG. 1B.
Referring to this figure, the second input signal line 107 is constituted by the third input signal line 109 and the fourth input signal line 110, and when both have a logic value "O", the first output signal line 10
The logic state of 2 is propagated onto the second output signal line 108 as is. When the third input signal line 109 has a logic value "1", the logic state of the second output signal line 108 has a logic value "o".
”, the third input signal line 109 has a logic value “O” and the output signal line 108 has a logic value “1” of the input signal line 110.
The logical states of all are logical "1". Usually, two or more logic circuits shown in FIG. 1 exist on one printed board. This relationship will be explained using FIG.

Now, there are two LSI chips 100' on one printed board.
, IO' is assumed to be implemented.

No matter what logic value the first output line 102', which is the output of the first logic circuit 103' of the first LI chip 100', takes, the second input signal line 107 as described above
Logic values that are all "O" or "1" depending on the value of are outputted onto the second output signal line 108'. The signal No. 2 is input to the first logic circuit 103'' of the second LSI chip 100, and is also input to the third logic circuit 104''.

This third logic circuit 104'' is preferably an 0R circuit if all the input signals have a logical value of 0;
1'', an AND circuit is suitable, and if the input signal is an odd parity signal, an exclusive OR circuit is suitable. If the predetermined value is not input, a logic value "1" is output on the third output signal line 105. This logical value "1" is output on the line between the second output signal line 10t8 of the first LSI chip 100' and the first input signal line IOV of the second LSI chip IO'. Failure, for example, disconnection due to defective bonding, or failure of the second LSI chip I
It is either a failure of the third logic circuit of O'. , Figure 3 shows the first example in which three of these LSI chips are simply connected in series, and the third output signal line of one LSI chip is connected to the first input of a non-adjacent LSI chip. A second example (B) of connection as a signal line is shown.

In both the first example (2) and the second example (B), the second input signal line is configured so that the same signal can be input to each LSI chip.

This means that each 01 chip 1001, 1002, and 10
03 second output signals 1081, 1082, and 10
This is to set all 83 to logical value "o" or "1".

Second output signal 1081, 108 of the previous stage LSI chip
2, is the first input signal 1012 of the subsequent LSI chip,
1013, and third output signals 1052 and 1053, which are the outputs of the exclusive OR, are output to the OR circuit. As a result, all the output signals for each printed board will be "O", and if there is no failure, the output will be "O". This is the lamp 1 connected to the OR circuit through the connection line 117.
Do not turn on 18. If one of them is faulty, the third output signals 1051, 1052, and 1053
The part in which the failure occurs has a logic value of "1", and the output of the OR circuit has a logic value of "1". This result display lamp 1
18 is lit. This lighting indicates a failure for each package. Note that a NAND circuit is used instead of the OR circuit to generate the third output signals 1051, 1052 and 10.
53 may all be set to "1".

FIG. 4 illustrates another embodiment of the present invention that includes the detection of faults between connections between printed circuit boards.

Now, in order to understand another embodiment, one plate 1. The number of LSI chips mounted on the main board is three, but any number may be used as long as it is two or more.

In this embodiment, the u2 chip and the OR circuit have the same structure as in the previous embodiment.

The feature of this embodiment is that an exclusive OR circuit is mounted on the same printed circuit board.

This exclusive OR circuit functions as explained below.
That is, the first LSI on the first printed circuit board 20?1
The second output signal 1084 of the chip 1004 is input to the second LSI chip 1005 on the same board, and the second
The second LSI chip 100 on the printed circuit board 2082 of
Also input it to 8. In addition, the first printed circuit board 20
01 is input to the exclusive OR circuit 1141 on 01. Similarly, the second output signal 1085 of the second I-chip 1005 is input to the third LSI chip 1006 on the same board, and the third LSI chip 1009 on the second printed circuit board 2002 is input to the third LSI chip 1006 on the same board. and the exclusive OR 1141 circuit on the first printed circuit board 2001. Now, each LS on the first printed circuit board 2001
A common second input signal 1071 to the I chip and a common second input signal 1072 to each U chip on the second printed circuit board 2002 are transmitted to both boards 2001 and 2.
All outputs of each LSI chip on 002 are set to logical value "o"
It is a signal that makes either a logical value "1" or a logical value "1".

As a result, if there is a connection failure between each LSI chip including the connection between printed boards, the output of the exclusive OR will have a logic value of "1".
”. As a result, the display lamp 1 is
108 is lit to indicate a failure. Note that if the output of this exclusive OR is directly connected to another indicator lamp, it will be easier to detect the failure location. In addition, in this embodiment, the third logic circuit of the LSI chip: 5 is as follows.
Although it is included in the chip, it does not necessarily need to be included in the LSI chip, and it is sufficient if it is provided corresponding to each LSI chip. It may be provided centrally for each board.

'o From the above explanation, the first effect of the present invention is that failures in the bond portion of Π■ can be easily detected.

The main target area for failure detection is the failure of the bond part [In particular, the failure rate of the bond part is relatively high, so the present invention, which focuses on this part, is suitable for electronic data processing devices configured with LSI. is very effective. The second advantage of the present invention is that failures can be quickly detected on a board-by-board basis, making repairs extremely easy and quick. To explain the repair image using the previous example, if there is a failure in the electronic data processing device, the failure will occur due to an error display of the check function of the device itself, an abnormal termination of 0S, or an error display by the function test program. The maintainer is notified of the existence of the
The maintenance person immediately operates a switch connected to the second input signal to change the logic state between the LSIs to a logic value "O" or a logic value "1". If there is a failure in the bond part of the LSI, the lamp corresponding to the board where the failure exists is lit. The maintenance person replaces the board corresponding to the lamp, operates the above-mentioned switch again, and checks the lamp. If all the lamps are off, the repair is complete. A third effect of the present invention is that when designing an electronic data processing device to which the invention is applied, a logic designer does not need to take special consideration for the invention.

This is because the functions that the electronic data processing device should originally have and the failure detection function according to the present invention are taken into consideration independently.

[Brief explanation of drawings]

FIG. 1A is a diagram showing the configuration of a chip that is an embodiment of the present invention, FIG. 1B is a diagram showing a detailed circuit of the second logic circuit in FIG. 1A, and FIG. Figure 3 shows the relationship between logic circuits between chips on one board. Figure 3 shows an example where chips are mounted on one board. Figure 4 shows an example where chips on multiple boards are connected. This is a diagram. The symbols used in the figures will be explained below. 100, 100', 100'', 2001, 2002, indicate LSI chips, 101, 1?1', 10V, 1?
11, 1012, 1013 indicate the first input signal, 1
02, 102', 102'' indicate the first output signal;
03,103′,1?3″ indicates the first logic circuit;
04, 104', 104'' indicate the third logic circuit;
05,105',105'',1051,1052,10
53 indicates the third output signal, 107,10?1,10
72 indicates the second input signal, 108, 108', 10
8″, 1081, 1082, 1083, 1084, 10
85 indicates a second output signal.

Claims (1)

[Claims] 1. A logic device including a plurality of logic units to which a common control signal is input, wherein each of the plurality of logic units processes data supplied to the logic unit of the relevant stage to generate a first output signal. a first logic circuit that outputs, and a second logic circuit that selects either the first output signal or a predetermined output signal according to the control signal and outputs it as data to a subsequent logic unit.
and a logic circuit in which the predetermined output signal is inputted as data to the logic unit of the stage concerned, so that when the control signal is applied, if data is erroneously supplied, a logic value different from that when data is correctly supplied is generated. and a third logic circuit that outputs an output.