JPS6048823B2 - Counting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for counting the number of rotations in an electronic device having a rotating body, such as a magnetic recording/reproducing device.

In magnetic recording and playback devices J such as cassette tape recorders,
Generally, the amount of tape running is displayed using a frame-like tape counter, but in recent years, this tape counter has been replaced with an electronic counter and an electro-optical display device such as a liquid crystal display device has been adopted as the display device. Things are being thought of and put into practical use.

By the way, when the above-mentioned display device displays various other information in addition to the amount of tape travel, in other words, when the magnetic recording/playback device itself has a timekeeping function or arithmetic function, the internal circuit shows the amount of tape travel. In addition to counting the amount, various processes for obtaining time information or calculation information, and further operations for determining count contents for repeat play, etc., must be performed simultaneously. However, when each of these processes is performed by sequential control using a microprogram, especially when the tape is running at a high speed and a count pulse with a short cycle is output, the count pulse may be input while other functions are being controlled. There was a risk of a counting error. FIG. 1 is a time chart showing such a conventional example, and shows a pulse as shown in FIG. When this rotation period (1, 1, 1, etc.) is output, the counter in the device synchronizes with the rising edge of the pulse as shown in Figure 1b. perform counting operations,
Subsequently, judgment operations for repeat play, etc. are performed as shown in FIG.

However, as shown in Figure d, other processes such as counting
If the pulse is superimposed on the input pulse in a above, the counter cannot detect that a new input pulse has arrived, and in the end, it is assumed that the input as shown in e of the same figure has been received, and the result as shown in f of the same figure is generated. Obtain the count value. Note that this count value starts from "10". In this way, with conventional electronic counters, if input pulses and other processing such as counting overlap in time, counting for input pulses of "1" or "2" or more is difficult. However, the reliability of the tape counter may be lost. Therefore, in order to prevent such malfunctions, a method can be considered to separate the counting function section of the tape counter from other processing circuits and operate it independently, but such a method would complicate the circuit configuration. It has the disadvantage that it not only works, but also becomes expensive.

In addition, when a liquid crystal display device is used as the display device, it becomes difficult to read the displayed contents, especially when driving at high speeds such as fast forwarding or rewinding, due to the response speed of the liquid crystal display element. There was also a problem in that it was difficult to stop the tape running at a desired position, and the function as a tape counter could not be fully demonstrated.

On the other hand, the tape running mode of a magnetic recording/playback device can be divided into low-speed running for play or reverse and high-speed running for fast forward or rewind. Even if accurate operation can be achieved in other modes, malfunctions or unnatural displays may occur in other modes, making it difficult to develop a counting method that is accurate and easy to read in any mode. It was wanted.

The present invention has been made in view of the above circumstances, and is a counting method that detects in which operating mode the rotating body is operating, and performs rough counting in one mode and fine counting in the other mode. The purpose is to provide

In order to achieve the above object, the present invention sets the pulse period output from a pulse generator to n:1 with respect to the rotation period of a rotating body, detects the state of a specifying means for specifying a running mode, and provides a high-speed When running, a predetermined value is counted for each of the above pulse periods, and when running at low speed, a predetermined value is counted for each of the above pulse periods and the original rotation period of the rotating body predicted from this pulse period. An embodiment in which the present invention is applied to a magnetic recording/reproducing device having a timekeeping function will be described with reference to FIGS. 2 to 7.

That is, FIG. 2 shows a schematic configuration of this embodiment, and numeral 1 in the figure is a cassette tape.

This cassette tape 1 is mounted on a mounting section 2, and a pinch roller 4 is rotated by a capstan shaft 4a that follows the rotation of a motor 3 by a predetermined interlocking mechanism (not shown).
and reel shafts 5,,5. It is driven to travel by. Reference numeral 6 designates a first pulley 1 for rotationally driving a pulse generator 8, which will be described later. The rotation of the pulse generator 8 is transmitted by the belt 7 to a second pulley 9 provided on the pulse generator 8.

The diameter ratio of the first pulley 6 and the second pulley 9 is a:b (capstan shaft 4a or reel shaft 51).
, 52 and the second pulley 19 is n:1), forming a frequency divider by mechanical means. The pulse generator 8 is composed of a second pulley 9, a disc-shaped electrode 17 integrally configured, and a detector 11.
is in elastic contact with the periphery of the disc-shaped electrode 10. Further, the disc-shaped electrode 10 has an insulating portion provided on a portion 10a of its periphery, and at least its periphery is conductive, and this conductive portion is grounded via the rotating shaft. On the other hand, since the detector 11 is pooled up to a potential of +V (volts) via the resistor 12, the disc-shaped voltage base 1
As the detector 11 slides on its periphery due to the rotation of 0, logic ``1'' (+V) and ``0'' are generated.
'(ground) output is obtained. That is, this output is ``1'' when the insulating part 10a of the disc-shaped electrode 10 and the detector 11 are in contact, and it is detected when the peripheral edge (conductive) of the disc-shaped electrode 10 other than the insulating part 10a is detected. The period is ``0'' when the child 11 is in contact with the capstan shaft 4a or the reel shafts 5, 5. There is a relationship of n:1 with the rotation period of the pivoting part (abbreviated as "pivoting part").The output signal obtained from this detector 11 has a logic value of "0".
The signal is input to a one-shot circuit 13 which detects the rising edge from ``1'' to ``1'' and generates a one-shot trigger pulse. On the other hand, numeral 14 includes controllers 15a, 15b, 15c, and 15d that control high-speed time counting, low-speed time counting, timekeeping, and other functions, and controllers 15a to 15d that control the counting of each function. The trigger pulse output from the one-shot circuit 13 is passed through an AND gate 17 to a high-speed count controller 15a, and via an AND gate 18 to a low-speed count controller 15b. are applied respectively.

When this trigger pulse is applied, the high-speed count controller 15a gives a code generation command signal to the code generator 19 to generate a code signal of a predetermined value, and also outputs a counting command signal. is applied to one input terminal of the AND gate 20 as an opening/closing control signal. The other input terminal of the AND gate 20 also has a code signal "n" output from the code generator 19.
” is applied, and the AND gate 20 outputs a code signal of “n” every time the counting command signal is applied.
This code signal is passed through the OR gate 21 to the counting circuit 16.
given to. The low speed count controller 15b is
When the trigger pulse outputted from the one-shot circuit 13 is applied via the AND gate 18, counting of pulse intervals is started, and the operation continues until the next trigger pulse is applied. A code generation command signal and a counting command signal are sent to the code generator 19 similarly to the high-speed count controller 15a, which control the operation of predicting and counting the original rotation period of the drive unit based on the counted value of the interval. Output. The AND gate 27, to which this counting command signal is applied to one input terminal, outputs the output of the code generator 19, which is applied to the other input terminal, every time the counting command signal is applied. , the counting circuit 16 via the OR gate 21
give to Note that this counting circuit 16 includes a counter for measuring the amount of tape travel at high speed or low speed, as well as a time counter, etc., and each of these counters is connected to each controller 15a to 15d that controls the respective functions. controlled by. Further, 22 is a mode switch (play, fast forward, etc. button or a switch linked thereto) for selecting high speed driving mode or low speed driving mode, and its fixed contact 22a is connected to the high potential side +V ( Volt) and is applied directly and via the inverter 24 to the AND gates 17 and 18, thereby controlling the outputs of the AND gates 17 and 18. That is, when the movable contact 22b of the mode switch 22 is in an open state with respect to the fixed contact 22a, the input to the logic section 14 becomes +V (volt) (logic "'1"), and the AND gate 17 is opened and closed. When it is in the positive state, 0 (volt) (logic ``o'') is input to the logic section 14, and the AND gate 18 is opened, and high-speed counting and low-speed counting are respectively performed.On the other hand, The output of this mode switch 22 is also applied to a travel drive control section 25 that controls the operation of the rotation drive section, and the drive section is controlled by this travel drive control section 25 to change its travel speed as appropriate. The speed can be changed without electrical control using such a mode switch 22.
It is also possible to use mechanical means using a predetermined interlocking mechanism. Therefore, from the logic section 14, the above-mentioned counting circuit 16
The contents of the predetermined counters are appropriately selected and outputted and applied to the display section 26 to be displayed simultaneously or exclusively, and a control signal to the traveling drive control section 25 is also outputted.

Next, the specific configuration of the logic section 14 in FIG. 2 will be explained with reference to FIG. 3.

Note that since the logic section 14 in FIG. 2 is only schematically shown, new reference numbers will be added to the explanation in FIG. 3. That is, in FIG. 3, 31 is a ROM (read only memory) in which a microprogram that controls the operation of each circuit in the logic section 14 is fixedly stored. Row address designation signals [Ftl], [Su], various code signals [c] such as count data "n", column address designation signal [FNSL] that designates the processing column of the RAM 32, various operation commands [INS]. and a next address signal [NA] specifying its own next address are output in parallel, and the next address signal [NA] is sent to an address decoder 35 via an address modification circuit 33 and an address buffer 34.
is input. The address decoder 35 specifies the address of the ROM 3l based on input address information, and the ROM 3l and the address recorder 35 form a microprogram controller that performs sequential control over each circuit.
In addition, the row address designation signals "Fu" and "Su" output from the ROM 3l are sent to AND circuits 36 and 37, which are controlled to open and close by respective timing signals (the timing signals will be described later), to designate a column address. Signal [F
) SL] is a column address controller 3 including an address counter etc. that specifies and controls processing columns (so-called digits) of the RAM 32.
8, and the operation command [INS] decodes the contents of this command and outputs various control signals 0, to 0,. and an instruction decoder 39 which outputs a control signal to the column address controller 28. Further, the output of the code signal [c] is sent to an AND circuit 40 whose opening and closing are controlled by a control signal 0 outputted from the instruction decoder 39. On the other hand, as shown in detail in FIG. 4, the above W32 is composed of areas A to E (hereinafter referred to as registers) each having six digits and arranged in the row direction. ing.

Therefore, the 1st to 4th digits of register A store the count value that counted the amount of tape travel during high-speed or low-speed travel, and the 5th digit stores the predicted value during low-speed travel. A value counted by "1" is stored for each original rotation period of the rotating body, and the sixth digit is a start flag indicating that the first output is made from the one-shot circuit 13 during low-speed running. It is something to remember. Further, register B stores the count value of the interval between pulses output from the one-shot circuit 13 during low-speed running.
Register C temporarily stores the count value of the previous pulse interval in order to predict the original rotation period of the drive unit during low-speed running, and register D predicts the original rotation period from the count value of the pulse interval. It is used to do. Additionally, register E is a register used to perform timekeeping functions. Therefore, the designation of each register of the RAM 32 is determined by the collective output of the AND circuits 36 and 37, that is, by the row address designation signal [Fu] or [S
u] is applied to the row address input terminal [RAU] of the RAM 32.

Further, the column address outputted from the column address controller 38 based on the column address designation signal [F)SL] outputted from the ROM 31 is stored in the RAM 31 for the processing column (digit).
2 column address input terminals [RAL], and the RAM 32 applies these to each address input terminal [RAL].
Based on the address applied to [AU] and [RAL], data at that address is output from the output terminal [0UT]. In addition to the above addresses, the RAM 32 also contains timing signals and the above control signal 0. The output of the AND circuit 41 to which is applied is read/write control (R/W)
It is applied as a signal, and this R/W signal is '0'.
When it is ``1'', reading is being controlled, and when it is ``1'', writing is being controlled.
If the data is the contents of the register specified by the row address designation signal [Su], the data output from the buffer 42 to which the read clock T,·φ1 is applied, and the opening/closing control signal T ,・0.

is applied to the arithmetic circuit 44 via the AND circuit 43 to which
is sent to one input terminal a of the row address designation signal [F
Open/close control signal V-0 when the contents of the register specified by [u] are changed. is sent to the other input terminal b of the arithmetic circuit 44 via the AND circuit 45 to which is applied. In addition,
The AND circuit 45 receives the output of the AND circuit 40, that is, R
A code signal [c] output from the OM 3l is also applied, and is sent to the other input terminal b of the arithmetic circuit 44 in the same way as the data read out from the RAM 32. This arithmetic circuit 44 consists of an adder and its peripheral circuits that execute operations such as addition and subtraction under the control of the control signal q, and executes predetermined operations based on the zeta input from input terminals A and b. and outputs the result (data) and carry/borrow signal. The zeta output from the arithmetic circuit 44 is sent to the data input terminal [IN] of the RAM 32 and is also applied to the output decoder 46 and the OR gate 47.
'', the data applied to the data input terminal [IN] is written. Note that the address to be written in the RAM 32 is determined by the J address designation similar to the above reading. Further, the output tecoder 46 receives the above control signal 0. Based on the data sent from the arithmetic circuit 44, it outputs a control signal to the travel drive control section 25 shown in FIG. The data is sent to a display buffer 48 consisting of a plurality of correspondingly provided buffers. The display buffer 48 statically stores the display data sent from the output decoder 46, and its output is sent to a predetermined drive circuit (
(not shown) to the display section 26 shown in FIG. On the other hand, the output of the OR gate 47 is the control signal 07
The carry/hollow signal output from the arithmetic circuit 44 is directly applied to the carry/borrow side latch 49b of the judgment latch circuit 49.

Therefore, each latch 4 of this judgment latch circuit 49
The outputs JL and JH of 9a and 49b are connected to the OR gates 33a and 33b of the address modification circuit 33 via AND gates 50 and 51, respectively, whose opening and closing are controlled by the control signal 08.
, and modifies the next address signal [NA] output from the ROM 3l. Further, 52 is an oscillator composed of a crystal oscillator or the like that outputs a fundamental frequency for timekeeping, and the oscillation output is applied to a frequency divider 53 having a predetermined number of stages, and the frequency divider 53 receives a signal with a period of 1 second. (1 second signal) and output this 1
The second signal is applied to the one second latch 54 which stores that the second signal has been output.

The output of this one second latch 54 is the control signal 09.
It is sent to the OR gate 33c of the address modification circuit 33 via the AND gate 55, which is controlled to open and close by, and modifies the next address signal [NA] output from the ROM 3l, similarly to each output of the judgment latch circuit 49. Furthermore, the second
The output of the one-shot circuit 13 in the figure is applied as a set signal to a counting latch 56 which has the same function as the one-second latch described above, and the output of this counting latch 56 is connected to an AND gate whose opening and closing are controlled by the control signals 0 and 0 described above. applied to the OR gate 33d of the address modification circuit 33 via the gate 57;
The next address signal [NA] is modified in the same way as described above. Note that each of the latches 54 and 56 receives the control signal 0.
, , and 0, 2. Furthermore, the output of the mode switch 22 in FIG. ,
The address is modified in the same manner as the AND circuits 50, 51, 55, and 57 described above.

On the other hand, from a predetermined frequency division stage of the frequency divider 53, clock signals φ, φ, which drive each of the circuits described above are output.

are output, and these clock signals φ,,φ. is sent to the above circuit and also to the timing signal generation circuit 59.
will be sent to. This timing signal generation circuit 59 receives input clock signals φ, φ. The timing signals T2 and T3 are superimposed and output sequentially.
is output and sent to each of the gate circuits mentioned above, as well as to the instruction decoder 39. The reason why the timing signal generating circuit 59 generates the different timing signals is that in this embodiment, the RAM 32 operates in three phases as shown in Table 1. Next, the operation of the above configuration will be explained with reference to the flowchart of FIG. 5 and the time charts of FIGS. 6 and 7.

Note that t and Nt in FIG. 5 indicate the time required for the step or process, and t is the processing time for one cycle from tl to T3 shown in Table 1 above. Therefore, when processing multiple digits, the number of processed digits x t
This process requires a long processing time. Further, in this embodiment, for convenience of explanation, n will be explained assuming that n=4. First, with reference to FIGS. 5 and 6, a case will be described in which the mode switch 22 shown in FIG. 2 is in an open state and high-speed driving is instructed.

That is, in FIG. 6, a indicates the tape running instruction state, b indicates the rotation period of the capstan shaft or reel shaft, and c indicates the second
The output states of the one-shot circuit 13 in the figure are shown respectively, and the phase shift in b and c in the figure is due to the fact that the insulating part 10a of the disc-shaped electrode 10 is not in contact with the detector 11 at the starting point. It is caused by something.

However, now the time shown in Figure 6! If tape running is instructed at IA, as shown in FIG. 5A, each step is executed from "START" shown in FIG. Step S1 is to detect whether the counting latch 56 is set, that is, whether there is an output from the one-shot circuit 13 shown in FIG. However, since the AND gate 67 does not output until the counting latch 66 is set, this step S shown in FIG. 6f is repeated without address modification.
Therefore, time A shown in FIG. When the first pulse is output from the one-shot circuit 13 as shown in FIG. The process then proceeds to step S2. This step S2 is to reset the counting latch 56, and the control signals 0 and 2 are sent from the instruction decoder.
is output, and the process then proceeds to step S3. Step S3 is to add "n/2 (= February) to the first to fourth digits of the A register.
The address input terminals [RAU] and [RAL] of
The address specifying the register and column addresses 1 to 4 are [Su] of the ROM 3l and the column address controller 38
are outputted from A, ~, respectively. The contents (currently 0) are read out sequentially. Then, the data output terminal of RAM32 [0U
This data output from [T] is applied to one input terminal a of the arithmetic circuit 44 via the buffer 42 and the AND circuit 43, while the code signal [c] of the ROM 3l is
/2 (=February) is output, and this "n/2" is applied to the other input terminal b of the arithmetic circuit 44 via the AND circuits 40 and 45. and b
The input data is added (0+n/2 (=2)) based on the control signal 05 indicating addition given from the instruction decoder 39, and the result "2" is added again as shown in FIG. 6i. A register A of RAM32, ~
. write to. The reason why n/2 is added in step S3 is that the positional relationship between the insulating portion 10a of the disc-shaped electrode 10 of the pulse generator 8 and the detector 11 is uncertain at the start. Therefore, the highest probability n/
2 is added, and this step S. After completing step S. Proceed to. In step S4, the contents of the first to fourth digits of the A register are displayed in the display buffer 4.
8, and each address input terminal of RAM32 [
RAU] and [RAL] have A register and "1 to 4"
The data read out from the RAM 32 is subjected to appropriate processing via the arithmetic circuit 44, output decoder 46, etc., and applied to the display buffer 48, thereby displaying the display contents. becomes "2" as shown in FIG. 6j, and the process then proceeds to step S5. Step S5 determines whether the mode switch shown in FIG. This detects whether or not the vehicle is running at low speed, and the instruction decoder 39 outputs a control signal of 0. is output and applied to the AND gate 58. However, since the command is now to drive at high speed, this is step S. The result of the determination is ``YES'', that is, ``1'' is output from the AND gate 58 and applied to the OR gate 33e to modify the address, and then the process proceeds to step S6. Note that the above step S. ~S. The processing time is as shown in FIG. 6g. Step S6 detects the set state of the one-second latch 54 by an operation substantially similar to step S1, and the instruction decoder 39 outputs a control signal of 0. is output and gate 5
However, since the 1-second latch 54 is in the reset state as shown in FIG.
Proceed to step 7. In step S7, the set state of the counting latch 56 is detected by the same operation as in step S, but since the counting latch 56 is now in the reset state as shown in FIG. There is no output, and the judgment result is "NO", and the next step S8
Proceed to. Step S8 detects the state of the mode switch 22 by the same operation as step S5, but since it is currently in the open state, the AND gate 58 outputs '1', and the determination result is If you say "YES", then step S. Steps S6 to S continue until the next one-second latch 54 or counting latch 56 is set. is repeatedly executed as shown in FIG. 6f. However, the 6th
At time A3 shown in the figure, a trigger pulse is output from the one-shot circuit 13 as shown in figure c, and when the counting latch 56 is set as shown in figure d, this set state is detected in step S7, and the next The process then proceeds to step S9. Step S9 does not actually perform any processing, but is executed to prevent errors in counting pulse intervals in the low-speed mode, which will be described later. Then, the second digit is read and written, and then the process advances to step SIO. Step SIO is step S above. This resets the counting latch 56 in the same way as in Step SIO.
Proceed to. Step Sll is the same as step S5 mentioned above, and now it is judged as "YES" and the next step Sll is
Proceed to step 2. Step Sl2 operates almost the same as step S3, and in the case of high-speed running, the output period of the one-shot circuit 13 is n with respect to the rotation period of the drive section.
(=4):1, this n (=
4), and the code signal [c] of ROM3l
outputs "4" and the arithmetic circuit 44 outputs A register A, . This is done by adding ``6'' to the 6th
As shown in FIG. Proceed to. Step Sl3 is the step S described above. It is similar to A register A1~,
The content "6" is sent to the display buffer 48 and displayed on the display section 2.
6 is displayed as "6" as shown in FIG. 6j, and then the process returns to step S6. The processing time from step S8 to step Sl3 is as shown in FIG. 6g. In this way, during high-speed driving, it is detected in steps S6 to S8 whether either the one-second latch 54 or the counting latch 56 is set, and when it is detected that the counting latch 56 is set, Ste Nobu S9~S
13 is executed to add (count) "n (=4)" to the A register. and A
, when it is detected that the counting latch 56 is set as shown in FIG.
As shown in j, i becomes "10" and "14". However,
The process at time A5 described above is completed, and the process proceeds to step S.

~S, is being executed at time A shown in FIG. Then, the one second latch 54 is set, as shown in FIG. Step S. is for resetting the one-second latch 54, and this operation is performed by the control signals 0, , output from the instruction decoder 39 in substantially the same manner as in step S2 above, and the process then proceeds to processing SB. This process SB performs various processes for timekeeping, and R
The time measurement information stored in the E register in the AM 32 is read out, and the arithmetic circuit 44 adds "+1" to the 1 second digit, and other advancement processing or 1212? Processing etc. are also performed within this processing SB. Therefore, when this process SB is completed, time measurement information is stored in the E register in the RAM 32 in a predetermined format, and the process then proceeds to step Sl5. Step Sl5 is the step S described above. and S. Similarly, the currently designated mode is determined by the same operation as described above, and now the result is ``YES'' and the process returns to step S6 to repeat steps S6 to S8. After this timing processing, time A shown in FIG.
,,A. One-shot circuit 1 as shown in c and d of the same figure.
There is a pulse output from 3, and when the counting latch 56 is set, the time A is reached. Steps S6 to Sl
3 as appropriate, and the A register and its display state are shown in I of the same figure.
, j, they are "18" and "22".

In this way, when driving at high speed, the rotation period of the drive unit is n
: Add "n" based on this frequency division ratio every cycle of 1 (count)
Therefore, there is no risk of a counting error even if the operation is controlled by a single microprogram controller along with other processing such as timekeeping processing, and there is no risk of counting errors, and it is easy to read the displayed contents. It is also easier to

Next, with reference to FIGS. 5 and 7, a case will be described in which the mode switch 22 shown in FIG. 2 is in the closed state and low-speed running is instructed.

In addition, for the purpose of simplifying the explanation, the above-mentioned high-speed driving condition is used. For each step explained in , only the step number will be described and a detailed explanation of the invention will be omitted. Further, b and c in FIG. 7 have exactly the same relationship as b and c in FIG. 6. That is, first, at time B shown in FIG. 7, a tape running instruction is given as shown in FIG. 7A, and when the tape runs, time increases.

The above steps S are continued until the counting latch 56 is set as shown in d of the figure. However, time B. When this happens, the counting latch 56 is set and then step S is performed. ~
S. Execute the A register and its display state as shown in the figure I.
, j, the value becomes "2" and the process then proceeds to step S5. Step S5 is to detect whether the mode switch 22 is open or closed as described above, and since the mode switch 22 is currently open, the AND gate 58 is
Since there is no output from and address modification is not performed, the detection result is "NO" and the process proceeds to step Sl6. Step Sl6 writes "1" to the 6th digit of the A register, that is, the start flag digit, as shown in FIG. The code signal [c] (=“1”) is output from the ROM 4l, and this code signal “1” is output from the ROM4l.
'' is applied to the other input terminal b of the arithmetic circuit 44 via AND circuits 40 and 45. Further, address designation signals indicating the A register and the 6th digit are applied to each address input terminal [RAU] and [RAL] of the RAM 32, respectively, and when the timing signal T3 is output, the code signal "1" is output.
is written to the 6th digit of the A register, and then step S
Proceed to l7. Steps S, . . . are stored in the B register storing the count value of the pulse interval.
. , S, , is added to the data 18tIn (t is set in advance) for 1/n (n=4) of the total processing time of , and is added to the row address input terminal [RAU] of the RAM 32. The address corresponding to the B register is [
RAL] are sequentially applied with addresses "1 to 6" from the column address controller 38 to read out the contents of the B register, and the code signal [c] of the ROM 3l is "18".
tIn'' is output, and each of these data is applied to terminals a and b of the arithmetic circuit 44, respectively. That is, the instruction decoder 39 in the arithmetic circuit 44
Control signal 0 output from. The addition is instructed by , and the result is written into the B register of the RAM 32 again, and then the process proceeds to step S,8. Step Sl8 is
The counting latch 56 is
This is to detect the set state of , and since it is not currently set, the process advances to step Sl9. Step Sl9 is
Step S, similar to step S, above. ,S,. and step S, which will be described later. 1/n of all processing time of O
The operation is the same as step Sl7 above. After completing this step Sl9, the next step is step S. The process proceeds to step S, and it is determined whether the one-second latch 64 is set. However, since the one-second latch 54 is not set now, the process returns to step Sl8 and steps Sl8 to SI are repeated to accumulate the processing time 1/n. Then, at time B3 in FIG. 7, there is a second output from the one-shot circuit 13, and when it is detected that the counting latch 56 is set, step S. The judgment result is “YES”.
'', the address is modified in the address modification circuit 33, and the process then proceeds to step S2l. This step S2l is
The counting latch 56 is reset in the same manner as step S2 above, and after this process is completed, the next step is step S. . Proceed to. Step S22 is to clear the 6th digit of the A register, that is, the start flag.
By executing Step 2, the content of Yo-kun shown in Figure 7 f becomes "O".
The process then proceeds to step S23. Step S23 is to add "n - 1 = (3 months) to the first to fourth digits of the A register, and the operation is to add the contents of the A register read from the RAM 32 in substantially the same manner as shown in step S3.
This is done by adding the code signal [c] (=3) of the ROM 4l to "1" in the arithmetic circuit 44, and as a result, the stored content of the A register becomes "5" as shown in FIG. 7i. Next, proceed to step SM.

In step S2, "n-1 (=
This is used to write the month of March, and it is used to set how many predictive counts are to be performed based on the pulse interval count stored in the B register. However, this Ste I Knob S. , and then step S. . Proceed to. Step S5
And the next step S26 is to transfer the value of the previous pulse interval counted by the B register to the C register, which is an auxiliary register, and the D register, which obtains data for predictive counting, respectively. Then ROM3l
The row addressing signal [Su] of
] is performed by pointing the C register, step S. . This is done by specifying [Su] to register C and [Fu] to register D, respectively. When this step S26 is completed, the process proceeds to step S2, and step S. ,S,. ,S. ,~S. , and step S described below. . ,S. . Add 1/n (n=4) of the total processing time 40t to the B register. This addition is performed in the same manner as steps S, , S, and 9 except that the code signal [c] of the ROM 3l outputs "40tIn", and when the process is completed, the next step is step S. ，
Proceed to. Step S28 subtracts the count value of the previous pulse interval transferred in step S26 from the D register at n times the speed of adding (counting) it to the B register.
The code signal [c] of ROM3l outputs "40t",
This is done by supplying a control signal indicating subtraction to the arithmetic circuit 44, and upon completion of this process, the next step is step S. . Proceed to. Step S. 9 is "1" in A register
is added, and the code signal [c] of ROM3l
outputs "1", the calculation circuit 44 executes the addition, and then the process proceeds to step Sl3.

Step Sl3 is to send the first to fourth digits of the A register to the display buffer 48 as described above, and these are steps S29 and S. As a result of executing , the A register and its display state become "6" as shown in FIG. 7I, j. That is, this time B. Since the capstan shaft 4a) or the reel shafts 51, 52 rotates four times between the time and the above time (2), this "4" is added (counted) as a result in the steps S23 and S29. Then, the above step S. After completing step S. ,S,
is executed in the same manner as above, and then the process proceeds to step S8. In this step S8, since the mode switch 22 is closed, a "NO" result is obtained, and the process then proceeds to step S3O. Step S3O is the step Sl
9. Step S similar to S27. ~S. and step S, which will be described later. ,,1/n of the total processing time of ST 16t
(n=4) is added to the B register, and when this process is completed, the process proceeds to step Sal. Step S3,
Detects whether the fifth digit of the A register is "O" or not, and the memory contents of A5 are applied to the judgment latch circuit 49 via the arithmetic circuit 44, and the address is modified based on the set state. However, since the stored content is "3", the answer is "NO" and the process advances to step S32.

Step Sp is basically step S. . and step S. ~S. and S. O-S. . The entire processing time of ``16U'' is subtracted, and whether or not the result is ``O'' or less is determined by the same judgment operation as in step S3l above, and if the result is ``1'' or more. If so, return to step S6 again and hold the latch 5 for 1 second.
The steps S6 to S8 and SO to S32 are repeated until it is detected in step S6 or step S7 that either the count latch 56 or the counting latch 56 is set. If, at time B4 shown in FIG. 7, the determination result in step S32 becomes "YES" as shown in g in FIG. 7, then the process proceeds to step S0. Step S33 subtracts [1] from the fifth digit of the A register.
The stored content of 5 becomes "2" as shown in FIG. 7h, and the process then proceeds to step S3l. Step S34 is to set the count value of the previous pulse interval again while adding the contents of the auxiliary memory I8, that is, the C register, to the D register whose memory content has become "0" or less. By doing this, even if the value becomes "0" or less in step S32, the amount is corrected (that is, the processing time for the negative part is also taken into consideration) and the process proceeds to step S35.
Step S35 and the next step S36 are similar to steps S27 and S28, and step S3
3-S36 and 1/1/27t of processing time in Sl3
n (n=4) and 27t are respectively added and subtracted, and after completing this step S36, the next step S36 is completed.
29 and Sl3 are executed, and the A register and its display state become "7" as shown in FIG. are repeated sequentially. Therefore, at times B5 and B6 shown in FIG. 7, the determination result in step S32 described above becomes "YES" as shown in g in the figure, and step S3
After executing steps 3 to S36, S29, and Sl3, the stored contents of the 5th digit of the A register are "1" and "1" as shown in h of the figure.
0", and the 1st to 4th digits of the A register and the display status also change to "8" and "9" as shown in Figures 1 and j.
and returns to step S6 again. Then, steps S6 to S8 and S3O are executed to perform step Sl3l.
, the memory contents of the 5th digit of the A register are shown in Figure 7h
As shown in the figure, it is "0", so the judgment result is "Y".
ES" and then proceeds to step S37. Step S
37 does not substantially operate at all, but simply reads and writes the first to sixth digits of the A register, and in addition to the processing time of step S32, the next step The process returns to S6, and thereafter steps S6 to S8, S3O, S3l, and S37 are repeated in sequence. Then, at time B7 shown in FIG. 7, the counting latch 56 is set by the output of the one-shot circuit 13, and the process advances from step S7 to step S6, and steps S9 and SlO are executed in the same manner as described above. Next step S
Proceed to ll. As a result of "NO" is obtained in step Sll, the next step S24 to S2 is
9 and Sl3 are executed in the same manner as above, and the A register and display state become "10" as shown in FIG. 7, 1, j, and A
5 stores "3" and then returns to step S6. Thereafter, as shown in FIG. 7, at times B8 and B9, the same operation as explained at times B4 to B8 is performed, and the A register and its display state are changed to "11" as shown in FIG. 7, 1 and j. ”
, "12". Next, the one second latch 54 is set at the time shown at 7 in FIG. The operation after IBIO will be explained.

Note that the A register and display will be “4” before this time BIO.
Assume that it has become the moon. That is, until it is detected that the 1-second latch 54 is set in step S6, one of the above-mentioned loops is selectively executed, and now, at time BLO shown in FIG. When the latch 56 is set, this set state is detected in step S7, and then steps S9 to Sll, S24 to S29 and S
Execute l3, and the A register and display status are as shown in Figure 7 1, j
As shown in FIG. 3, the value becomes "42" and the process returns to step S6 to execute a predetermined process. Then, time B shown in FIG.
When the 1 second latch 54 is set at ll as shown in d of the same figure,
In step S7, the set state of the one-second latch 54 is detected, and then step Sl4 and processing SB are executed, and the process then proceeds to step Sl5. It is assumed that the processing time of this processing SB is At as shown in FIG. and,
In the mode detection at the next step Sl5, a "NO" result is obtained, and the process then proceeds to step S38. Step S38 is
The state of the 6th digit of the A register, that is, the start flag, is detected in the same manner as in step S3l, but now the stored content is "0" as shown in FIG. 7f. , the result of the above detection is determined to be "NO", and the process then proceeds to step S39. Step S39 is the step S39 described above.
6, Sl4, Sl5, S38, S39 and S4 described later
Further, 1/n (n=4) of S4l or S42 and all the processing time (a+17)t of the above processing SB is added to S1 to S6 of the B register, and this processing is performed in accordance with the above step Sl7 etc. Similarly, step S
Proceed to 4O. Step S4O is similar to step S3l above, and it is determined whether the fifth digit of the A register is "0" or not. However, now the above step S24
Since [n-1 (=3)] remains set, the result of the judgment in step S4O is "NO", and the process then proceeds to step S, l. Here, this step S4l is at time 2 shown in FIG. If so, step S above
6. The result of subtracting the total processing time "(a+17)t" of Sl4, Sl5, S38 to S4l and processing SB is "0" or less, and the judgment result is [YES], and the process proceeds to step S33, and the series of steps described above are performed. Steps S33 to S36
, S29, and Sl3 are executed, and the register A and display state become "43" as shown in FIG. 7, 1, j. Next, step S
Return to 6. If the result of the judgment in step S4l is "NO", that is, the result of subtracting "(a117)t" from D1 to D6 is "1" or more, the process returns directly to step S6, and the process returns to step S6 directly. The judgment result in S4O is [YES]
”, step S4 for time adjustment is performed, which is exactly the same as step S37 above. is executed, and then the process returns to step S6. As has become clear from the above explanation, by executing any of the steps described above, the storage contents and display state of the A register will be changed to "44", " 45” and “46”. On the other hand, if it is detected in step S2O that the 1-second latch 54 is set between times B2 and B3 in FIG. 7, that is, while steps Sl8 to S2O are being repeatedly executed, Next step Sl4
Then, the process SB and step Sl5 are executed, and the process proceeds to step S38. Therefore, in this state, the sixth digit of the A register is "1" as described above, and the determination result is "YES" and the process proceeds to step S43. Step S43 is step S, i, Sl5, S
38, S43 and processing SB all processing time "(a+9
)t'' is added to the B register, and the operation is performed in the same manner as in step Sl7, etc., and then the process returns to step Sl8, and then the counting latch 56 is set. Steps Sl8 to S2O are repeated until it is detected in Step Sl8 that the When the counting latch 56 is set, the above-mentioned processes are then executed to perform appropriate calculation and time measurement processes. In this way, when driving at low speeds, the original rotation period of the drive unit is predicted based on the previous pulse interval, and counting is performed based on this prediction, so the pulse generation means for counting is exactly the same as when driving at high speeds. Despite the configuration, the count is as if it were 1.
:Natural counting can be performed as in 1, and there is no risk of a counting error even if time-sharing control is performed using the only microprogram controller along with other processing such as timekeeping processing. .

In the above description, the present invention is applied to a magnetic recording and reproducing device having a timekeeping function, but the present invention is not limited to this, and can be applied to a magnetic recording and reproducing device having an arithmetic function such as a small electronic calculator. It can also be applied to a magnetic recording and reproducing device having a timekeeping function and arithmetic function.

Further, in the above embodiment, the period ratio of the pulse output to the drive section was explained as 4:1, but this can be any ratio, and preferably the maximum time for controlling the operation (the total of Nt according to the above explanation) can be set to any ratio. ) or more, the counting becomes reliable.

Furthermore, in the above embodiment, the case where the number of rotations of the drive unit is counted has been described, but this is not limited to the number of rotations;
For example, it is possible to count the traveling length according to the rotation, and various other deformation reactions are possible without departing from the gist of the present invention.

As explained in detail above, according to the present invention, the output period of the pulse generator for counting is set to 1:n with respect to the rotation period of the drive section such as the capstan shaft or the reel shaft, and the operation mode of the drive section is In the first mode, a predetermined value is counted each time a pulse is generated from the pulse generator, and in the second mode, the count is performed every cycle predicted based on the output cycle of the pulse. By performing 7 counts each with a predetermined value, two counting modes can be used with the same configuration, and the counting can be performed without error even if it is a sequential control with other processing. Furthermore, it is possible to provide a counting system that can satisfy the requirements of the two operating modes, such as the display being easily readable.

[Brief explanation of the drawing]

FIG. 1 is a time chart for explaining the conventional method, FIG. 2 is a schematic configuration diagram for explaining an embodiment of the present invention, FIG. 3 is a detailed view of the main parts in FIG. 2, and FIG. Fig. 4 is a configuration diagram of the RAM in Fig. 3, Fig. 5 is a flowchart for explaining the operation in Fig. 3, Fig. 6 is a time chart for explaining the operation during high-speed running, and Fig. FIG. 7 is a time chart for explaining the operation during low speed running. 3...Motor, 4a...Capstan shaft, 8...Pulse generator, 13...One-shot circuit, 14...Logic section , 22・
...Mode switch, 31...ROMl3
2...R. AMl44... Arithmetic circuit, 54
...1 second latch, 56...counting latch.

Claims (1)

[Scope of Claims] 1. In an electronic device that performs predetermined counting according to the original rotation period of a rotating body and also performs other processing other than this counting process, mode selection means for changing the rotation period of the rotating body. and pulse generating means for generating a pulse with a period divided by 1/n from the rotation period of the rotating body, and a timing of 1/n time of the period of the pulse outputted from the pulse generating means from the previous time. timing prediction means for predicting based on the pulse period; and when the first mode is selected by the mode selection means, counting by n or a predetermined value based on n depending on the pulse output from the pulse generation means; However, when the second mode is selected by the mode selection means, the number of rotations of the rotating body or the rotation is adjusted according to the pulse output from the pulse generation means and the timing predicted by the timing prediction means. A counting method comprising a counting means for counting by a predetermined value based on the number of rotations of the body, and performing the other processing described above between the pulses divided by the frequency of 1/n. 2. In claim 1, the rotating body is a capstan shaft or reel shaft of a magnetic tape reproducing device, and the counting means counts every few rotations of the capstan shaft or reel shaft according to a mode selection by the mode selection means. Alternatively, a counting method is characterized in that a predetermined value is counted for each original rotation period predicted every several rotations. 3. In claim 1, the rotating body is a capstan shaft or reel shaft of a magnetic tape reproducing device having a timekeeping function, and the counting means is included in a single microprogram controller that controls the timekeeping function. A counting method characterized in that the counting method is controlled by a microprogram stored in common with a microprogram, and counts by a predetermined value every several rotations of the capstan shaft or reel shaft by selecting a mode of the mode selection means. 4 In claim 1, the rotating body is a capstan shaft or reel shaft of a magnetic tape reproducing device with a small electronic calculator equipped with a timekeeping function, and the counting means is a small electronic calculator equipped with a timekeeping function. It is controlled by a microprogram stored in a single microprogram controller that controls the computer, and is predicted every few revolutions or every few revolutions of the capstan shaft or reel shaft by selecting the mode of the mode selection means. A counting method characterized by counting by a predetermined value for each original rotation period. 5. In claim 1, the mode selection means selects between two modes, a high speed mode and a low speed mode, and the counting means selects a high speed mode when the mode selection means selects the high speed mode. The calculation is performed in increments of "n" according to the pulse output from the pulse generation means, and when the mode selection means selects the low speed mode, the pulse output from the pulse generation means and the timing predicted by the timing prediction means are calculated. A counting method that is characterized by counting in increments of 1 according to the number of seconds.