JPS6022740B2 - Counting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for counting the number of rotations in an electronic device having a rotating body, such as a magnetic recording/reproducing device.

Magnetic recording and playback devices such as cassette tape recorders generally display the amount of tape travel using a mechanical tape counter, but in recent years, this tape counter has been replaced with an electronic counter, and the display device uses a liquid crystal display, for example. Devices employing electro-optical display devices, such as devices, have been considered and put into practical use.

By the way, when the above-mentioned display device displays various other information in addition to the tape running amount, in other words, when the magnetic recording and reproducing layer itself has a timekeeping function or arithmetic function, the internal circuit does not display the tape running amount. In addition to counting the distance traveled, various processes for obtaining time information or calculation information, and further operations for determining count contents for repeat play, etc., must be performed simultaneously. Therefore, when each of these processes is performed by sequential control using a microprogram, especially when the tape running speed is far and a count pulse with a short period is output, the count pulse may be output while other functions are being controlled. There was a screen blind that caused a counting error when the number was entered. FIG. 1 is a time chart showing such a conventional example, and shows a pulse as shown in FIG. When this rotation period is a rotation period of 1 or less such as 1, 1/2, 1'4, etc.), the counter in the device detects the rising edge of the pulse as shown in Figure 1b. The counting operation is performed periodically, and the judgment operation for repeat play, etc. is performed as shown in Figure c.
This is done as shown below.

However, as shown in Figure d, if other processes such as timekeeping are performed in conjunction with the input pulse in a above, the counter cannot detect that there is a new input pulse, and as a result, Assuming that there is an input as shown, a count value as shown in f of the figure is obtained. It is assumed that this count value starts from "10". In this way, in the case of a conventional electronic counter, if the input pulse and other processing such as timing processing are temporally delayed, the counter will not respond to input pulses of "1" or "2" or more. There were cases where counting could not be performed, and the reliability of the tape counter was lost. Therefore, in order to prevent such malfunctions, the counting function section of the tape counter was separated from the other processing circuits.
A method of operating the device independently is conceivable, but such a method not only complicates the circuit configuration but also makes it expensive.

The present invention has been made in view of the above circumstances, and is based on pulses whose frequency is divided by 1/n with respect to the rotation period of a rotating body, and a predetermined value is counted at each predetermined interval within the pulse output interval. The purpose of this study is to provide a counting method that does this.

In order to achieve the above object, the present invention provides a system in which the speed change from the rise of the rotating body to the constant speed state and from the constant speed state to the stop is approximately linear, and the pulse output period is the same in the constant speed state. Focusing on the fact that The running length, etc. according to the rotational speed is counted, and counting is performed based on periodic pulses with a frequency division ratio of 1/2 for the rotating body, with reference to Figures 2 and 3 below. A first example of the case will be described.

That is, in FIG. 2, 1 is a cassette tape, and this cassette tape 1 is mounted on a mounting section 2, and a capstan shaft is connected to the rotation of the motor 3 by a predetermined interlocking mechanism (not shown). The pinch roller 4b rotated by the reel shaft 4a and the reel shafts 5, 52 drive the reel. In addition to the interlocking mechanism for the capstan shaft 4a and the like mentioned above, the motor 3 is provided with a first pulley 6 directly connected to the motor shaft for rotationally driving a pulse generator 8, which will be described later. The rotation of the first pulley 6 is transmitted by a belt 7 to a second pulley 9 provided on a pulse generator 8 . In this embodiment, the ratio between the first pulley 6 and the second pulley 9 is a:b (the rotation ratio between the capstan shaft 4a or the reel shafts 5, 52 and the second pulley 9). (2:1), and a 1/2 frequency divider is constructed by mechanical means. The pulse generator 8 is composed of a second pulley 9, a disc-shaped electrode 10, and a detector il, which are integrated with each other, and the detector 11 is in elastic contact with the periphery of the disc-shaped electrode 10. In addition, an insulating portion is provided on a portion 10a of the periphery of the disk-shaped electrode 1, and at least the periphery thereof is conductive, and this conductive portion is grounded via the rotating shaft. On the other hand, since the detector 11 is pooled up to a potential of 10 V (volts) via the resistor 12, the rotation of the disc-shaped electrode 10 causes the detector 11 to move relatively around its circumference. Logic “1” (
10V) and "0" (ground) outputs are obtained.

That is, this output is "1" when the insulating part 10a of the disc-shaped electrode 10 and the detector 11 are in contact, and when the output is "1" when the insulating part 10a of the disc-shaped electrode 10 is in contact with the periphery (conductive) other than the insulating part 10a. Detector 1
1 is in contact, and its period is in a 2:1 relationship with the rotation period of the capstan shaft 4a or the reel shafts 5, 52. Therefore, the output signal obtained from this detector 11 changes from logic "0" to "
1" and generates a one-shot pulse (having a time width equivalent to one word of the first counter 14, which will be described later). The output of this one-shot circuit 13 is It is input to the first counter 14 as its clear signal.
is output from the basic clock generator 15 which operates based on signal A indicating that the device is in operation. The output (count contents) is input to the register 17 via the AND gate 16 whose opening/closing is controlled by the output of the one-shot circuit 13.

The clear signal input to the counter 14 is configured so that the actual clearing is performed after the contents of the counter 14 are input to the register 17 described above. Therefore, the output of the register 17 is the basic clock generator 15.
The clock signal output from the subtracter 19 is applied via the AND gate 18 to one input terminal a of a subtracter 19, which is supplied to the other input terminal b, and the output of this subtracter 19 is inputted to the register 17 again. . On the other hand, the borrow signal output from the subtracter 19 is input as a count signal to the second counter 21 via the OR gate 20 together with the output of the one-shot circuit 13, and is also input to the set terminal S of the R-S flip-flop 22. Applied as a set signal. Further, the output of the one-shot circuit 13 is applied to the reset terminal R of the R-S flip-flop 22, and the reset side output Q of this R-S flip-flop 22 is applied to the AND gate 18 as an opening/closing control signal. .
By the way, in the above configuration, for counting the second and subsequent pulses output from the one-shot circuit 13,
It is possible to predict the original rotation period of the capstan shaft 4a or reel shafts 5, 52 from the previous pulse output synchronization and perform accurate counting, but the period between the first and second pulses is output. In the first cycle, there is no previous data for prediction, and it is necessary to correct this in some way to prevent errors from occurring in the count.

Therefore, as a method for this correction, the first output from the one-shot circuit 13 is normally "11".
However, when the second shot is output, the count value to be predicted for the first period is counted all at once.

(2) A method of counting all the count values that should be predicted in the first cycle when the first output is received from the one-shot circuit 13.

■ At first, the count is kept as it is, and then it is corrected when the tape stops running.

However, in the case of this embodiment, the method (2) above is realized by each of the circuits 23 to 25.

That is, the output of the one-shot circuit 13 is output from the AND gate 23.
The signal is applied to a binary counter 24 having a 1-bit configuration. Then, the output of this binary counter 24 is the second
The "11" command is applied to the counter 21 of the R-S flip-flop 25, and the R
-S flip-flop 25 is the binary counter 24
It is set at the falling edge of the output when the output is inverted from "1" to "0". In addition, the reset terminal R of the R-S flip-flop 25 is connected to the “E” signal that is output when the tape stops running.
The set side output Q is applied to the AND gate 18, and the reset side output Q is applied to the AND gate 23 as opening/closing control signals. Therefore, the second counter 21 is connected to the OR gate 20 and the binary counter 2 when there is a second output from the one-shot circuit 13.
It is configured such that it receives the "11" command from both of the 4 and executes the "12" command. The output of the second counter 21 is sent to the display section 26 via a predetermined processing circuit (not shown), and the contents of the second counter 21 are displayed as the amount of tape travel. ing. Next, the operation in the above configuration will be explained with reference to the time chart of FIG. 3.

In FIG. 3, a indicates the rotation period of the capstan shaft 4a or reel shaft 5, 52, and b indicates the rotation period of the capstan shaft 4a or reel shaft 5, 52. , 52, respectively, show the output states of the one-shot circuit 13 which outputs pulses at a period divided by 1/2 from the rotation period of the motors. In addition, the figure c shows the clock signal ◇ output from the basic clock generator 15.
d indicates the same clock signal ◇/2, respectively. When the tape is instructed to run and the first trigger pulse is output from the one-shot circuit 13 at time L', the output is sent to the OR gate 20 as shown in FIG. 3g. The signal is applied to the second counter 21, and the count value of the second counter 21 becomes "1" as shown in FIG. 3k'. On the other hand, the output of the one-shot circuit 13 is applied to the first counter 4 as a clear signal, and is also applied to the AND gate 16, so that the previous count value (0) of the first counter 14 is stored in the register 17. As a result of the transfer, the stored contents of the first counter 14 and the register 17 become "0", respectively, as shown in FIG.
In addition, the output of the one-shot circuit 13 is applied to the binary counter 24 via the AND circuit 23, which sets the binary counter 24 to "1" (the R-S flip-flop 25 is not set) and the reset terminal of the R-S flip-flop 22. The Q outputs of these R-S flip-flops 22 and 25 are shown in FIG.
The result will be as shown below.

Therefore, the first counter 14 starts counting based on the clock signal 2 from time t, as shown in FIG. It can be continued until Note that the AND gate 18 between these times is the R-S flip-flop 2.
Since its output is prohibited by the Q side output of 5, the stored contents of register 7 remain unchanged. When the time reaches Ut2, a pulse is output from the one-shot circuit 13, and the output is applied to the second counter 21 via the OR gate 20, and the binary counter 24 is inverted by the output of the AND gate 23. 1”→
“0”) and the “11” command is given to the second counter 21, so that the count value of the second counter 21 becomes the third
As shown in figure k, it becomes "3" and the R-S flip-flop 2
5 is set. Also, at this time, the count value of the first counter Yubuki turtle is "Yu" as shown in FIG.
will be forwarded to.

The count value “Yu” transferred to register 7 is subtracted by subtractor 19.
The clock signal ? from the AND gate 18 is input to the other input terminal b of the ? , the first counter 14 is subtracted to "0" twice as fast as shown in FIG. A borrow signal is output as shown in FIG. 3e. This borrow signal is applied to the second counter 21 via the OR gate 20 as shown in FIG. "become. Also, the output of the borrow signal at this time causes an R-S flip.

Since the input pin 22 is set and its reset side output Q becomes "0" as shown in FIG. In addition, “x” in Figure 3 i
” indicates the result of subtraction “0-1”. Then, at the next time t4, when the one-shot circuit 13 outputs an output as shown in FIG. 3b, the count value of the second counter 21 becomes "5" as shown in FIG. The flip-flop 22 is reset and its reset side output Q becomes "1" as shown in FIG. Further, the count value of the first counter 14 from time ratio 3 to t4 is "m",
This count value "m" is transferred to the register 17 via the AND gate 16, and is sequentially incremented by one in the subtracter 19 each time the clock signal is output.

Therefore, when the time ratio becomes 5, the subtractor 19 outputs the value e in Figure 3.
The borrow signal is outputted as shown in FIG. S flip-flop 22 is set.
In this way, in this embodiment, the current output is changed from the previous output of the one-shot circuit 13 which outputs a trigger pulse with a period divided by 1/2 with respect to the rotation period of the capstan shaft 4a or the reel shafts 5, 52. By counting up to the output of
As is clear from the progress up to the time ratio of 5, the speed of the capstan shaft 4a or reel shaft 5 is not constant.
Although there is a slight time lag between the predicted original rotation period and the rotation period of . Then, from time t to t, 4, the same operation as described above is repeated sequentially, and the count value of the second counter 21 becomes "7" to "15", and "especially the capstan shaft 4a or the reel shaft". In the next period after 5. and 52 are running at a constant speed, that is, after time 5, the predicted original rotation period completely corresponds to the actual rotation period.In this way, In this embodiment, by predicting and counting the original rotation period from the previous period of the pulse whose period is divided by 1/2 with respect to the rotation period of the pinch roller 4 or the reel shaft, the relatively slow pulse period is calculated. Therefore, it is possible to accurately perform counting based on the original rotation period of a relatively fast rotating body.

Above, capstan shaft 4a or reel wisteria 5, 52
The first embodiment has been described in which the period of the pulse output from the one-shot circuit 13 is divided by 1'2 with respect to the rotation period of the capstan shaft 4a or the reel shafts 5, 52. For one-shot circuit 13
The second case where the period of the pulse output from is 1/n
An example of this will be described with reference to FIG.

In order to simplify the explanation, the same parts as in FIG. 2 are given the same reference numerals and the explanation thereof will be omitted. That is, in this embodiment, by setting the period of the pulse output from the one-shot circuit 13 to the rotation period of the capstan shaft 4a or the reel shafts 5, 52 to be n:1, the first counter 14 is applied with the clock signal G/n output from the basic clock generator 15, and its output is applied to the AND gate 16.
The signal is sent to the auxiliary register 27 via the auxiliary register 27.

This auxiliary register 27 is used to update and store the contents of the first counter 4 as soon as a pulse is output from the one-shot circuit 13, and its output is sent to an OR gate 29 together with the output of the AND gate 16 via an AND gate 28. The output of OR gate 29 is applied to register 17, which has the same function as the register in FIG. On the other hand, the borrow signal output from the subtracter 19 is applied to a delay circuit 30' having a time delay necessary to transfer all the contents of the auxiliary register 27 to the register 17, and the output of this delay circuit 30 is "n- The signal is applied to the third counter 31 of 1' base and also applied to the OR gate 20. Further, the output of the one-shot circuit 13 is applied as a clear signal to this third counter 31, and when the count value reaches "n-1", "1" is output from this third counter 31.
” is output.

However, the output of the lever is applied to the AND gate 18 via the inverter 32, and the AND gate 18 is closed when the count value of the third counter 31 reaches "n-1". . Therefore, in this embodiment, within one cycle of the pulse output from the one-shot circuit 13, "n-1" borrow signals are output from the subtracter 19 every 1/n of the previous cycle. It is structured as follows. That is, if the count value of the first counter 14 in the previous one cycle was "T", this "T" is transferred to the auxiliary register 27 and the register 17 when the one-shot circuit 13 outputs an output. and set. And is the memory content “T” of register 17 a clock? The subtractor 19 adds "
The first counter 14 becomes ``0'' in a time 1/n of the time it takes to count up to ``T'', and the next clock 0 is output, and the subtracter 19 generates a borrow signal. However, when a borrow signal is output from the subtracter 19, this signal is applied to the OR gate 20, the AND gate 28, and the third counter 31 via the delay circuit 30, respectively.
The second counter 21 and the third counter 31 each read "11", and the register 17 is again set to the storage content "T" of the auxiliary register 27. Then, such operation continues until the count value of the third counter becomes "n-1", and finally, before the next pulse is output from the one-shot circuit 13, the subtracter 19 outputs "n". -1'' times the borrow signal is output and applied to the second counter 21. Therefore, the operation in this example can be easily inferred from the time chart (Figure 3) of the above example by setting the output of the borrow signal in the above example to "n-1" times. Therefore, the details will be omitted.

In this way, in this embodiment, the period of the pulse outputted from the one-shot circuit can be set as desired with respect to the rotation period of the capstan shaft 4a or the reel shafts 5, 52, in an n:1 relationship. Even so, it is possible to perform extremely accurate counts. Above, the first example and the second example
Each embodiment of the counting method according to the present invention has been explained by way of embodiments. Next, a third embodiment in which the counting method according to the present invention is applied to a magnetic recording and reproducing device having a timekeeping function will be described in FIGS. 5 to 5. This will be explained with reference to FIG.

Incidentally, in the configuration of this embodiment, reference numbers 1 to 13 in FIGS. 2 and 4 are exactly the same as those described above, and therefore, description of those portions will be omitted. That is, FIG. 5 is a block diagram of a logic section that performs a timekeeping function and a counting function in this embodiment. In the figure, numeral 41 indicates a microprogram that permanently stores a microprogram that controls the operation of each circuit, which will be described later. This is a ROM (read only memory), and from this ROM41,
A row address designation signal Fu for the RAM 42, which will be described later.
Su, various code signals C, column address designation signals F and SL that designate processing examples of the RAM 42, various operation commands INS, and a next address signal NA that designates its own next address are output in parallel, respectively. Next address signal N
A is input to an address decoder 45 via an address modification circuit 43 and an address buffer 44. The address decoder 45 reads the ROM based on the input address information.
The ROM 41 and address decoder 45 perform sequential control for each circuit. A microprogram controller is formed to perform the functions. Further, the row addressing signals Fu and Su outputted from the ROM 41 are sent to AND circuits 46 and 47 whose opening and closing are controlled by timing signals t and t, respectively (the timing signals will be described later). SL is sent to a column address controller 48 including an address counter that specifies and controls processing columns (so-called digits) of the RAM 42, and an operation command INS follows the contents of this instruction to send various control signals ○, to ○. , 2 and an instruction decoder 49 which outputs control signals for the column address controller 28, respectively.
Further, the output of the code signal C is sent to an AND circuit 5 whose opening and closing are controlled by the control signals ◯ and ◯ output from the instruction decoder 49. On the other hand, Kamisou RA
As shown in detail in FIG. 6, M42 is composed of areas AB to E (hereinafter referred to as registers) each having six digits and arranged in the row direction. Therefore, the 1st to 4th digits of register A store the count value that counted the running distance of the tape, and the 5th digit stores the count value for each predicted original rotation period of the rotating body. The register B stores the value and also stores a start flag indicating that the first output has been made from the one-shot circuit 13 to the sixth digit sub-digit. It stores the count value at intervals of , and corresponds to the first counter 14 in FIGS. 2 and 4.

Register C is an auxiliary memory and corresponds to the auxiliary register 27 in FIG. 4, and register D stores the count value for predicting the original rotation period of the rotating body. Corresponds to register 17. Furthermore, register E is a register for performing a timekeeping function and stores timekeeping information. Therefore, the designation of each register of this RAM 42 is as follows.
Collective output of the AND circuits 46 and 47, that is, ROM4
1 row address designation signal Fu or Su is input to the RAM 42.
is applied to the row address input terminal RAU of .

Further, the processing column (digit) is determined based on the column address designation signals F and SL output from the ROM 41, and the column address output from the column address controller 48 is stored in the RAM 42.
Based on the address applied to each address input terminal RA and RAL, the RAM 42 outputs the data at that address from the output terminal OUT. , RAM
42, the output of the AND circuit 51 to which the timing signals and the control signal 02 are applied in addition to the above addresses is applied as a read/write control (R/W) signal, and this R/W signal is , when it is “0”, read out,
When it is "1", writing control is being performed. In addition to the data output from the output terminal OUT of the RAM 42, if the data is the content of the register specified by the row address designation signal Su, the read clock t,
, and the buffer 52 to which is applied, the opening/closing control signal t
. AND circuit 55 to which 04 is applied
The signal is sent to the other input terminal b of the arithmetic circuit 54 via the input terminal b.
Note that the AND circuit 55 receives the output of the AND circuit 50,
That is, the code signal C output from the ROM 41 is also applied, and is sent to the other input terminal b of the arithmetic circuit 54 in the same way as the data read from the RAM 42.

This arithmetic circuit 54 consists of an adder and its return circuit that executes operations such as addition and subtraction under the control of the control signal 05, and executes predetermined operations based on data input from input terminals a and b. Then, the result (data) and the carry IJ-borrow signal are outputted.
The data output from 4 is the data input terminal m of RAM42.
and the display processing circuit 56 and the OR gate 57
is applied to the data input terminal IM, and the RAM 42 writes the data applied to the data input terminal IM when the above-mentioned RW signal is "1". Note that the address to be written in the RAM 42 is specified by the same address specification as in the above-mentioned reading. Also,
The display processing circuit 56 is controlled by the control signal Q and converts the input data into display data based on the data sent from the arithmetic circuit 54, and converts the input data into display data using a plurality of buffers provided corresponding to each display digit. The data is sent to a display buffer 58 consisting of. The display buffer 58 statically stores the display data sent from the display processing circuit 56, and its output is sent to a display section (not shown) via a predetermined drive circuit (not shown). . On the other hand, the output of the OR gate 57 is applied to the data side latch 59a of the judgment latch circuit 59 controlled by the control signal 07, and
The carry-no-borrow signal output from the carry-no-borrow signal is released to the carry-no-borrow side latch 59b of the direct judgment latch circuit 59.

Therefore, each latch 5 of this judgment latch circuit 59
The outputs J and JH of 9a and 59b are connected to the OR gates 43a and 43b of the address modification circuit 43 via AND gates 60 and 61, which are controlled to open and close by the control signal 08, respectively.
and modifies the next address signal NA output from the ROM 41. Further, 62 is an oscillator composed of a crystal oscillator or the like that outputs a fundamental frequency for timekeeping, and its oscillation output is applied to a frequency divider 63 having a predetermined number of stages. (1 second signal) is applied to the 1 second latch 64 which stores the fact that this 1 second signal has been output.

The output of this one-second latch 64 is sent to the OR gate 43c of the address modification circuit 43 via the AND circuit 65 whose opening and closing are controlled by the control signal Q, and is output from the ROM 41 in the same way as each output of the judgment latch circuit 59. modifies the next address signal NA to be sent. Furthermore, the output of the one-shot circuit 13 in FIGS. 2 and 4 is applied as a set signal to a counting latch 66 which has the same function as the one-second latch, and the output of this counting latch 66 is applied to the control signal ○. , o is applied to the OR gate 43d of the address adjustment circuit 43 through the AND gate 67, which is controlled to open and close by the signals NA, and modifies the next address signal NA in the same manner as described above. Note that each of the latches 64 and 66 receives the control signal ○.
、． and 08. - Also, from a predetermined frequency division stage of the frequency divider 63, a clock signal , 2 is outputted for driving each of the above circuits,
With each of these clocks,? 2 is sent to each of the above-mentioned times and is also sent to the timing signal generation circuit 68.

This timing signal generation circuit 68 receives the input clock signal...? 2, timing signals t, , etc. and t3 are outputted sequentially without overlapping each other, and are sent to each of the gate circuits described above, as well as to the instruction decoder 49. The timing signal generation circuit 68 generates the timing signals L to t3 because the RAM 42 in this embodiment operates in three phases as shown in Table 1. Table 1 Next, the operation of the above configuration will be explained with reference to the flowchart of FIG. 7 and the time chart of FIG. 8.

Note that t and nt in FIG. 7 indicate the time required for the step or process, and t is the processing time for one cycle of t, . . . shown in Table 1 above. Therefore, when processing a plurality of digits, a processing time equal to the number of digits to be processed x t is required. Further, in this embodiment, for convenience of explanation, n will be explained assuming that n=4. That is, if the tape is instructed to run as shown in FIG. 8A during the hour shown in FIG. 8, each step is executed from "START" shown in FIG.

This step S detects whether or not the counting latch 66 is set, that is, whether there is an output from the one-shot circuit 13 in FIGS. 2 and 4. Control signal ○,. However, since the AND gate 67 is not involved until the counting latch 66 is set, the address is not modified and steps S are repeated. When the first pulse is outputted from the one-shot circuit 13 as shown in FIG. 8b with a time width of 2 shown in FIG. The signal is applied to the OR gate 43d of the address modification circuit 43, and the process then proceeds to step S2. This step S2 is for resetting the counting latch 66, which is accomplished by outputting the control signals ◯ and 2 from the instruction decoder 49, and the process then proceeds to step S3. In step S3, "1" is placed in the first to fourth digits of the A register.
is added to each address input terminal RA of RAM turtle 2.
The address specifying the A register and column addresses 1 to 4 are output from the ROM 41aSu and the column address controller 48 to U and RAL, respectively, and the contents of A, to 4 (
0) are read out sequentially. This data output from the data output terminal OUT of the RAM 42 is applied to one input terminal a of the arithmetic circuit 54 via the buffer 52 and the AND circuit 53, while the code signal c of the ROM 41 is set to "1". This "1" is applied to the other input terminal b of the arithmetic circuit 54 via AND circuits 50 and 55.

The arithmetic circuit 54 adds the data input from each input terminal a and b based on the control signal Q indicating addition given from the instruction decoder 49 (01).
Then, the result is stored in A of RAM 42 again as shown in Fig. 8h.
,~4. When this addition (counting) process is completed, the process proceeds to step S4. Step S4 is
The 8th digit is placed in the 6th digit of the A register, that is, the start flag digit.
As shown in FIG.
") is output, and this code signal "1" is output to the AND circuit 5.
0 and 55 to the other input terminal b of the arithmetic circuit 54. In addition, each address input terminal RAU of the RAM 42
Address designation signals indicating the A register and the 6th digit are applied to and RAL, respectively, and when the timing signal t3 is output, the code signal "1" is the 6th digit of the A register! After this is written, the process proceeds to step S5.

Step S5 is B which stores the count value of the pulse interval.
1/1 of the processing time from step S to this step S5 and all the processing time of step S6, which will be described later, is stored in the register.
Data corresponding to time n (n=4) is 19/n (in addition,
t is preset).
The address corresponding to the B register at the row address input terminal RA 2 is applied to the RAL, and each address from 1 to 6J is sequentially applied from the column address controller 48 to read the contents of the B register, and the code in the ROM 41 is Signal c is “
This is done by outputting "1 hole/n" and applying these data to the a and b terminals of the arithmetic circuit 54, respectively.
That is, the instruction decoder 4 in the arithmetic circuit 54
The addition is instructed by the control signal 05 output from 9, and the result is written into the B register of the RAM 42 again, and then the process advances to step S6.

Step S6 is to send the contents of the first to fourth digits of the A register to the display buffer 58.
The A register and each address specifying "1 to 4" are input to the address input ports AU and RAL, and the RAM
The data extracted from 42 is subjected to appropriate processing via an arithmetic circuit 54, a display processing circuit 56, etc., and then sent to a display buffer 5.
8, the display content becomes "1" as shown in FIG. 8i, and the process then proceeds to step S7. In step S7, the set state of the counting latch 66 is detected by the same operation as in step S, and since the counting latch 66 is not set now, the process proceeds to step S8. Step S8, like step S5, adds 1'n of all the processing times of steps S7, S8, and step S9, which will be described later, and its operation is the same as step S5.

When step S8 is completed, the process proceeds to step S9, where it is detected whether the one second latte 64 is set. This detection is performed by substantially the same operation as step S above, and the instruction decoder 49 outputs the control signal 09, but since the one second latch 64 is not set now, step S7 is performed again. Return to step S7-S9 and repeat steps S7 to S9 to save 1/1 of the processing time.
n is accumulated. However, the time in Figure 8'T3
When it is detected that there is a second output from the one-shot circuit 13 and that the counting latch 66 is set, the judgment result in step S7 becomes "YES", and the address modification circuit 43 modifies the address. and then step S, o
Proceed to. This step S. is the 6th digit of the A register,
That is, the start flag is cleared, and by executing steps S and o, the content of A6 becomes "0" as shown in FIG. 8e, and then steps S, . Proceed to. Step S, . is the 1st to 4th digit 1 of the A register "n-1=
(3)'', and its operation is substantially the same as shown in step S3, in which the code signal c (=3) of the ROM 41 is added to the content ``1'' of the A register read from the RAM 42 by the arithmetic circuit 54. As a result, the contents stored in the A register become as shown in FIG. 8h, and the process then proceeds to step S,2. This step S is for resetting the aircraft counting latch 66 in step S2, and when step S2 is completed, the process proceeds to step S3.

In step S, 3, "n-1 (=
3), which sets how many predictive counts are to be performed based on the pulse interval count stored in the B register. After completing step S, 3, step S, 4 and step S, 5 are executed in the same manner as step S3 and step S6, and A
The register and display state is as shown in FIG. 8h and i, and the process then proceeds to steps S and 6. This step S, 8 and the next step S, 7 correspond to setting data from the first counter 14 to the register 17 and the auxiliary register 27 in FIG. R
The row address designation signal Su of OM41 causes the B register to
This is performed by u designating the C register, and steps S and 7 are performed by Su designating the C register and Fu designating the D register, respectively. This step S
, 7, the process proceeds to steps S, 8, and 1/n (n 4) of all four processing times of steps S, S, o to S, 8 and steps S, 9, which will be described later, are stored in the B register. Set to . This process means that the code signal c of the ROM 41 is "4".
The same operations as steps S5 and S8 are performed except for outputting "enemy/n", and when the processing is completed, the process proceeds to steps S and 9. Steps S and 9 subtract the count value of the previous pulse interval transferred in steps S and 7 at n times the speed of addition (counting) to the B register.
The code signal c of 1 outputs "4 melon" and the arithmetic circuit-54
This is done by applying a control signal 05 indicating subtraction, and when this process is completed, the next step S is executed. In step S2o, the presence or absence of the set state of the one-second latch 64 is detected by the same operation as in step S9, but since the one-second latch 64 is not currently set, the determination result is "NO". Then, the process proceeds to step S2.

Step S2. is to detect whether the counting latch 66 is set or not, as in steps S, S7 above, but since the counting latch 66 is not set, the determination is "NO" and the next step is Proceed to step S22. The step S foundation is to add 1/n (n=4) of the processing time 15t of all steps S2o to S22 and steps S23 and S to be described later to the B register, as in the step S2 described above, and this process ends. Then, the process advances to step S23. Step S23 detects whether the fifth digit of the A register is "0" or not, and the memory contents of A5 are applied to the judgment latch 59 via the arithmetic circuit 54, and based on the set state. This is done by modifying the address, but since the memory content is "3",
If the answer is NO, the process proceeds to step S24. Step S24 is basically the same as steps S and 9,
The total processing time from step S2o to step S is 15
t'' and whether the result is less than or equal to 0 is determined by the same judgment operation as in step S23, and if the result is greater than or equal to 1, the process is performed again. Returning to step S2o, the steps S to S are repeated until it is detected that either the one second latch 64 or the counting latch 66 is set. If, at time L shown in FIG. 8, the determination result in step S24 becomes "YES" as shown in FIG. Execute in the same manner as step S3 and step S6, etc.
The stored contents and display state of the A register are as shown in FIG. 8h and i, and the process then proceeds to step S27.

The step S illusion subtracts "1" from the fifth digit of the A register by adding "11" to the A register in step S25 based on the judgment result of step S24.
The stored content of 5 becomes "2" as shown in FIG. 8g, and the process then proceeds to step S28. Step S28 sets the contents of the auxiliary memory C while adding them to the D register whose memory contents have become "0" or less. Even if it is, the amount is corrected (that is, the negative processing time is also taken into consideration) and the process proceeds to step S.
Step S29 and the next step S3o are similar to steps S, 8 and S, 9 above, and step S
~Processing time in step S3o 1'n of 29 (n=
4) and 2) are added and subtracted. When step S2 is completed, the process returns to step S2o again and steps S2o to S2 are repeated in sequence. Therefore, the time setting shown in FIG. 8 and the time shown in FIG.
The judgment result at Tsuru is ``YES'' as shown in figure f, and steps S to S are executed to register the fifth register of A.
The stored content of the digit changes to "1J, 0" as shown in g of the same figure, and the 1st to 4th digits of the A register and the display state change to "7H" as shown in h and i of the same figure. The value changes to "8" and returns to step S again. And this step S2o
When the process proceeds to step S23 after executing ~S, the stored content of the 5th digit of the A register is "0" as shown in Figure 8g, so the judgment result is "YES". Next, proceed to Step S nails.

Step S3 does not substantially perform any operation, but only reads and writes the first to sixth digits of the A register, and steps S2o to S
This is to match the processing time of step S24, and when this step S is completed, the process returns to step S2o, and steps S2o to S momme and S3. Repeat sequentially. At time T7 shown in FIG. 8, the counting latch 66 is set by the output of the one-shot circuit 13, and the process advances from step S2 to step S. Step S3
2 is for adjusting the processing time, similar to step S3 above, and when this step S32 is completed, the process proceeds to step S, 2, and steps S, 2 to S. 9 in the same manner as above, the A register and display status are as shown in Figure 8h,
The process then proceeds to step S2o as shown in i. Thereafter, at time T8 and ~ shown in FIG.
The same operations as described in 4-L are performed, and the A register and its display state become as shown in FIG. 8h and i. next,
When the 1 second latch 64 is set as shown in FIG.
.

The subsequent operation will be explained. Note that the A register and display are at this time T. It is assumed that the value was previously "39". That is, the above step S2. Until it is detected that the 1 second latch 64 is set in step S2o~
S number, S2o to S3. Or S2o ~ S general and S3,
Processing by one of the loops is being executed, and now,
Time T, shown in FIG. When the counting latch 66 is set, this set state is detected in step S2, and then steps S32 and S,2 to S,9 are executed, and the A register and display state are as shown in FIG. 8h, i. As shown, steps S2o to S24 are repeated again. Then, during the time shown in FIG. When the 1 second latch 64 is set as shown in c in the same figure, step S2 in the above loop is executed.
The set state of the one-second latch 64 is detected, and the process then proceeds to step S33. Step S33 is a 1 second latch 6
4, and its operation is performed in step S2 above.
The instruction decoder 49 sends control signals ○, . The process then proceeds to processing SB. This processing SB performs various processing for timekeeping, and the RAM
This processing SB reads out the timing information stored in the E register in the 42 and converts it to the digit of 1 second using the arithmetic circuit 54. Other processes such as 6G ship processing or 12/2 public transport processing are also performed within this processing SB. It is being done. It is assumed that the processing time of this processing SB is at as shown in FIG. 8d.

When this process SB is finished, next step S3
Proceeding to step S4, the state of the 6th digit of the A register, that is, the state of the start flag, is detected in the same manner as in step S23, but now the stored content of A6 is "0" as shown in FIG.
”, the result of the above detection is determined to be “NO” and the process proceeds to step S. In step S35, 1/n (n=4) of the processing time (a + 16) t of steps S33 to S35 described above, S36 described later, S or S38 and the above processing SB is stored in the B register. B of
, ~6, and the process is performed in step S5 above.
The process is performed in the same manner as above, and then the process advances to step S36. Step S$ is similar to step S23 above,
It is determined whether the fifth digit of the A register is "0" or not.

However, since "n-1 (=3)" is still set in step SB, the result of the judgment in step S is "NO", and the process then proceeds to step S. Here, if this step S37 is at time T, 2 shown in FIG. 8, the result of subtracting the total processing time "(a+16)t) of steps S33 to S37 and processing SB" is "0". The result of the judgment is "NO" and the process proceeds to step S25, where the above-described series of steps S25
~S3. is executed and the register A and display status are as shown in Figure 8h.
, i becomes "41" and then returns to step S Fox. Note that the result of the judgment "NO" in step S37 above, that is, the result of subtracting "(a116)t" from D, ~6, is "
1'' or more, the process returns to step S2o without performing the series of processes from step S25 onwards, and if the determination result in step S36 is ``YES'', the process does not proceed at all from step Sq. A similar process for time adjustment is performed and then the process returns to step S2o. As has become clear from the above explanation, the subsequent times T, 3 to T in FIG.
, 5, by executing any of the steps described above, the storage contents and display state of the A register become "42", "
43” and “44”.

On the other hand, during the time UT2 to T3 in FIG. 8, that is, while steps S7 to S9 are being repeatedly executed, the latch 6 is
When it is detected in step S9 that 4 has been set,
The process proceeds from step S9 to step S, after which processing SB is executed, and the process proceeds to step S34. However, in this state, as mentioned above, the 6th digit of the A register is "1".
", and the judgment result is "YESJ", and the process proceeds to step S39. Step S39 is step S39.
33, S34, S39 and processing SB.
1'n (n=4) of "(a18)t" is added to the B register, and the operation is performed in the same manner as in step S5, and then the process returns to step S7. In addition, in this example, the case with a timekeeping function was explained, but
For example, even if there is a judgment and process such as repeat play, it is clear that it can be performed using substantially the same steps or processes as described above.

In addition, ``In this embodiment, we have described a case that only has a timekeeping function, but for example, a case that has a calculation function in addition to this,
Alternatively, it goes without saying that the same operation as above can also be carried out for a device to which arithmetic functions are added alone.

In this way, in this embodiment, in order to count the amount of tape travel in the magnetic recording/playback device, the pulse input to the logic section has a relatively slow period of rotation relative to the rotation period of the rotational drive section of the capstan shaft or reel shaft. However, since the original rotation period that should exist during that period is predicted by counting the previous pulse interval, accurate counting is possible, especially when other functions are added.

In addition, since the amount of tape travel can be accurately counted using relatively slow pulses (separated with respect to the rotation period of the rotary drive section) as in this example, it is possible to control other functions and the amount of tape travel described above. It is possible to perform a sequential controller by sharing a single microprogram controller without performing parallel processing with the count of , which simplifies the configuration and reduces costs.

In the first to third embodiments described above, based on the pulses having a 1:n relationship with the rotation period of the rotating body, the rotation is performed at the original rotation period that should exist between the pulses and the pulses. Although the case has been described in which the number of rotations of the rotating body is counted, the present invention is not limited to this, and the traveling length may be counted according to the rotation of the rotating body.

Further, in each of the above embodiments, the case where the present invention is applied to a magnetic recording/playback device or a magnetic recording/playback device having other functions has been described, but the present invention is not limited to this, and the It goes without saying that the present invention can be widely applied to various electronic devices that count running lengths based on numbers, and that various other modifications and applications are possible without departing from the gist of the present invention.

As explained in detail above, in the counting method according to the present invention, the output period of the pulse generator for counting is set to 1:n with respect to the rotation period of the capstan shaft or the IJ-rule shaft, and this pulse By counting the pulses output from the generator and a predetermined value at each predetermined interval within this pulse output interval, the counted value is as if it were 1:1 with the rotation period of the capstan shaft or reel shaft. Since the counted value is a predicted cycle based on the previous pulse output interval, it can be displayed even in the case of an unstable cycle immediately after or just before the rotation of the rotating body starts or stops. Accurate counting is possible, and accurate counting is also possible even when there is disturbance in the rotation period due to power supply fluctuations, load fluctuations, etc.

In addition, in the present invention, since the pulse interval accepted by the counting function section is relatively wide, it is possible to control other functions during that time, and the circuit configuration can be simplified. have

[Brief explanation of the drawing]

Fig. 1 is a time chart for explaining the conventional method, Fig. 2 is a block diagram for explaining the first embodiment of the present invention, and Fig. 3 is for explaining the operation in Fig. 2. 4 is a block diagram for explaining the second embodiment of the present invention, FIG. 5 is a block diagram for explaining the third embodiment of the present invention, and FIG. 6 is a block diagram for explaining the third embodiment of the present invention. Horizontal diagram of RAM in the figure,
FIG. 7 is a flow chart for explaining the operation in FIG. 5, and FIG. 8 is a time chart of the same. 3...Motor, 4a...Capstan shaft, 8...Pulse generator, 14...First counter, 17.
...Register, 19...Subtractor, 21.
...Second counter-27...Auxiliary register, 4
1...ROM, 42...RAM, 64...
...1 second latch, 66. ．． ．． ...Counting latch. Figure 1 Figure 6 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 8

Claims (1)

[Claims] 1. In an electronic device that performs a predetermined count according to the original rotation period of a rotating body and performs other processes other than this counting process,
Synchronized with the rotation of the rotating body and 1/1 with respect to its rotation period.
a pulse generating means that generates a pulse with a period divided by n; a timing predicting means that predicts the timing of 1/n time of the period of the pulse outputted from the pulse generating means based on the previous pulse period; and counting means for counting the number of rotations of the rotary body or a predetermined value based on the number of rotations of the rotary body according to the output of the pulse generation means and the timing predicted by the timing prediction means, A predetermined count is performed according to the original rotation period of the rotating body predicted based on the pulses whose frequency is divided by 1/n with respect to the rotation period, and the other processing described above is performed between the pulses whose frequency is divided by 1/n. A counting method characterized by the following. 2. The rotating body is a capstan shaft or a reel shaft of a magnetic recording and reproducing device, and a predetermined count is performed according to the original rotation period of the capstan shaft or reel shaft. Counting method. 3. The rotating body is a capstan shaft or reel shaft of a magnetic recording and reproducing device having a timekeeping function, and the counting means is controlled by a microprogram stored in a single microprogram controller that controls the timekeeping function. controlled and performing a predetermined count according to the original rotation period of the capstan shaft or reel shaft predicted based on pulses whose frequency is divided by 1/n with respect to the rotation period of the capstan shaft or reel shaft. A counting method according to claim 1. 4 The rotating body is a capstan shaft or reel shaft of a small electronic calculator or a magnetic recording and reproducing device with a small electronic calculator equipped with a timekeeping function, and the counting means is a small electronic calculator or a small electronic calculator equipped with a timekeeping function. It is controlled by a microprogram stored in the only microprogram controller that controls the formula calculator, and is predicted based on the pulse frequency divided by 1/n with respect to the rotation period of the capstan shaft or reel shaft. 2. The counting method according to claim 1, wherein a predetermined counting is performed according to the original rotation period of the capstan shaft or the reel shaft.