JPS6049339B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system, and particularly to a pipeline type microprogram control system.

FIG. 1 shows the architecture of a pipelined microprogram computer that achieves high speed by simultaneously executing a microinstruction and reading the next microinstruction to be executed.

To explain its operation using FIG. 2, first, since the machine cycle is periodic, the operation start point of the address controller 1 is used as a reference, and after a period of time, address 1 is output and the microprogram memory 2 is transferred to the microcontroller. Reading of instruction 1 is started. The time required to read a microinstruction from memory 2 is shortened. At the beginning of the next machine cycle, this microinstruction 1 is transferred to pipeline register 3.
is set to When the output of this register 3 arrives at the arithmetic unit 4 via a gate circuit or the like (transfer time 3), execution of the arithmetic operation begins. On the other hand, address controller 1 uses the calculation result from the previous machine cycle and pipeline register 3.
Based on the next address information contained in , address selection of microinstruction 2 to be executed next is started. Now, in the same machine cycle, when the operation by microinstruction 1 is completed (operation time), the result is transferred to the register or address controller 1 (transfer time 5).
The same operation is repeated, but in this case, the machine cycle is determined by max (ti+=2; ti+=5).

Usually, the speeds of the arithmetic unit 4 and the memory 2 are selected so that (+T2=chi+T4+ζ) to improve cost performance.

Such microprogram control methods have been advanced with the development of high-speed 1C.

However, recently, as memories and arithmetic units that operate at several tens of Ns have become commercially available, problems in implementation have appeared, and it has become clear that there are limits to speeding up. In other words, the transfer times Tl, t3, and t5 of the data and microinstructions mentioned above are determined by the wiring length and stray capacitance caused by the wiring rather than the delay caused by the IC, so it is not possible to expect the effect of speed improvement by increasing the speed of the IC. . For example, if a memory and an arithmetic unit are mounted on different boards and connected to each other with a driver and a receiver, a delay of 20 to 50 r1s will occur due to an increase in the wiring length and its stray capacitance. This value is close to the operating time of high-speed memory and high-speed arithmetic unit. The present invention has been made in view of the above circumstances, and its purpose is to provide a high-speed microprogram control system. A feature of the present invention is that when processing a branch instruction, it not only predicts the next microinstruction to be executed and reads it from memory and prepares it, but also executes it first, and when testing the branch condition, The purpose is to determine whether to use the result or read another microinstruction.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing one embodiment of the present invention, and FIG. 4 is a diagram for explaining its operation. In FIG. 3, 10 stores microinstructions! micro program memory, 1
1 is a vibe line register that temporarily holds a microinstruction read from the memory 10; 12 is an address register that holds the address of the memory 10; 13'' is a 5 arithmetic unit that executes a microinstruction from the vibe line register 11; 14 is a multiplexer that selects the address of the next microinstruction to be executed; 15 is an incrementer that adds 1 to the output address of address register 12; 16 is a comparator that compares address signals; A branch processing circuit 18 which determines the next process to be performed is an instruction address decoder which decodes the microinstruction from the vibe line register 11 and supplies control signals to each section.

The address signal on line 19 is also referred to herein as the current address, and the address signal on line 20 is referred to herein as the jump address. In FIG. 4, 1, 2, and 3 in the vibe line register represent microinstruction 1, microinstruction 2, and microinstruction 3, respectively.

Selection 1, selection 2, etc. in the memory cycle mean selection of the address of microinstruction 1, selection of the address of microinstruction 2, etc. Further, reading 1, execution 1, etc. mean reading microinstruction 1, executing microinstruction 1, etc., respectively. Further, MTl, KTl, etc. respectively mean transfer and decoding of microinstruction 1, transfer of arithmetic results obtained by execution of microinstruction 1, and the like. Next, the basic operation of this embodiment will be explained.

Referring to machine cycle T2 in FIG. 4, the contents of the register 11, that is, the microinstruction 1, are supplied to the arithmetic unit 13 and are also supplied to the instruction decoder 18, which is a control signal that determines the address of the next microinstruction to be executed. is generated.As mentioned above, note I river 0
If a high-speed arithmetic unit 13 is used, the time required to transfer a microinstruction from the register 11 to the arithmetic unit 13 will be approximately equal to the memory access time and calculation time. Therefore, this transfer time can be used to select the address of the next microinstruction to be executed under the control of the instruction decoder 18. That is, when transferring microinstruction 1, instruction decoder 18
provides a control signal to increment 15 to add one to the current address on line 19 and output the address of microinstruction 2 to multiplexer 14. Next, the instruction decoder 18 supplies a control signal for selecting the output of the increment 15 to the multiplexer 14 if the microinstruction 1 is not a branch instruction or the like.

When microinstruction 1 is transferred to arithmetic unit 13 and decoded,
The arithmetic unit 13 starts executing the microinstruction.

At this time, the instruction decoder 18 provides a control signal to the address register 12, so that the address of the next microinstruction 2 to be executed is set in the address register 12. In this way, the execution of microinstruction 1 and the reading of microinstruction 2 to be executed next are performed simultaneously, and when these are completed, one microstep is completed.
In the next machine cycle T3, the instruction decoder 18 first supplies a control signal to the vibe line register 11, so that microinstruction 2 is set in the vibe line register 11. As in the previous machine cycle, this microinstruction 2 is transferred to the arithmetic unit 13 and the address of the microinstruction 3 to be executed next is selected. At this time, the instruction decoder 1
8 supplies a control signal to the arithmetic unit 13 to transfer the arithmetic result of the microphone J mouth command 1. That is, as is clear from a comparison of FIG. 2 and FIG. 4, according to the present invention, the machine cycle is shortened to about 2 times 3. In this way, a machine cycle is divided into the first half and the second half, and the first half selects the address of the next microinstruction to be executed, transfers the microinstruction to be executed, and performs operations using the microinstruction executed in the previous machine cycle. If the speed is increased by transferring the result, reading the next microinstruction to be executed in the second half, and executing the microinstruction, it is generally expected that the execution of the branch instruction will still result in a time loss. According to this embodiment, this problem can be greatly alleviated, and does not impede speeding up in any way. First, it is assumed that among the microinstructions stored in the microprogram memory 10, a branch instruction is provided with a bit BAS that specifies a branch address.

When this BAS bit is “1”, this microinstruction specifies a jump address, and when it is “0”, it specifies a continuous address.When this BAS bit is executed, the probability of jumping to the jump address and the continuous By comparing the probabilities of executing the address, the programmer can decide in advance which one has a higher probability.In FIG. 4, it is assumed that microinstruction 1 is a branch instruction.

Assuming that the BAS bit of microinstruction 1 is 0 and a continuous address (that is, the address of microinstruction 2) is specified, microinstruction 1 is first read in machine cycle T1, and microinstruction 1 is read in machine cycle T2. The decoding and execution of microinstruction 1 and the prefetching of microinstruction 2 are performed. During this prefetch of microinstruction 2, the current address on line 19 (ie, the address of microinstruction 2) is compared in comparator 16 with the jump address on line 20. The comparator 16 outputs MACH=1 if they match, and outputs MACH=0 if they do not match. Now MACH=0. The branch processing circuit 17 is a BAS
ExcIusiveO of bit contents and output MACH
The branch processing circuit 17 supplies the output "0" to the instruction decoder 18. If the signal from the branch processing circuit 17 is "0", the instruction decoder 18 continues processing. That is, the machine cycle T3 is entered, and the result of microinstruction 1 is transferred, microinstruction 2 is executed, and microinstruction 3 is read ahead. Now, microinstruction 1 is a branch instruction, and by transferring the result of microinstruction 1, it is possible to know whether microinstruction 2 read ahead was correct or not. If it is correct, in machine cycle T4, the result of microinstruction 2 is transferred, microinstruction 3 is transferred, and microinstruction 3 is executed, and no processing is interrupted. On the other hand, if the prefetched microinstruction 2 is incorrect (that is, if the result of executing microinstruction 1 should have been to jump to the jump address), the instruction decoder 18 transfers the result of microinstruction 2 in machine cycle T4. Transfer decoding of microinstruction 3 is prohibited, and the microinstruction at the correct jump address is read. Next, microinstruction 1
The case where is a branch instruction and its BAS bit is ゜゜1゛ will be explained. Microinstruction 1 in machine cycle T1
is read out, and in machine cycle T2, microinstruction 1 is decoded and executed, and the microinstruction to be executed next is prefetched. At this time, the comparator 16 outputs MACH=0,
Since BAS=1 now, the branch processing circuit 17 supplies the output "゜1゛" to the instruction decoder 18. Therefore, the instruction decoder 18 sends a control signal to the multiplexer 14 to select the jump address on line 20. In this way, the microinstruction [phase] is read, and in machine cycle T3, the result of microinstruction 1 is transferred and the prefetch of microinstruction 3 is performed. If [phase] is correct, the microinstruction [phase] is executed in machine cycle T4.
transfer the result of [phase], execute microinstruction ◎, and prefetch microinstruction ◎. This state is shown in FIG. On the other hand, if the prefetched microinstruction [phase] due to the transfer of the result of microinstruction 1 is incorrect, the transfer of the result of the microinstruction [phase] and the transfer decoding of microinstruction (b) are performed in machine cycle T4. Prohibits reading of microinstruction 2 correctly.

In this way, by taking micro-instruction pre-reading one step further and pre-executing micro-instructions, even if the micro-program includes branch instructions, time loss can be greatly reduced and speeding up can be achieved.

Furthermore, since it is determined whether to adopt the execution result of the prefetched microinstruction or read out another microinstruction based on the execution result of the branch instruction, the correct execution result of the microinstruction can always be obtained. As described above in detail, the present invention can further speed up a high-speed microprogram control system in which the memory access time, calculation time, and transfer time are approximately the same, without any special increase in hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the architecture of a conventional microprogram-controlled computer system, FIG. 2 is a diagram for explaining the operation of the computer system shown in FIG. 1, and FIG. 3 is a diagram showing an embodiment of the present invention. 4 and 5 are diagrams for explaining the operation of an embodiment of the present invention. 10... Micro program memory 11... Vibration line register, 12... Address register,
13... Arithmetic unit.

Claims (1)

[Claims] 1 Within one machine cycle, the execution of a microinstruction and the reading of the next microinstruction to be executed are performed almost simultaneously, and the microinstruction read out in the previous machine cycle is transferred to the arithmetic unit and decoded almost simultaneously. In a microprogram-controlled device that transfers the result of an operation using a microinstruction executed in a machine cycle, if the microinstruction executed in the i-th machine cycle is a branch instruction, the When the predicted microinstruction is executed and the branch instruction is executed, the previously predicted microinstruction is found to be incorrect. A microprogram control method characterized by prohibiting the transfer of operation results using microinstructions.