JPS6049997B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control method for magnetic bubble memory, charge-coupled device CCD memory, etc., and more specifically to a method for selectively using unit storage areas (for example, information loops) in memory. be.

Mechanical rotation type memory devices such as magnetic drum memory devices and magnetic disk memory devices have conventionally been used as file memories in information processing devices. However, with recent advances in semiconductor technology, solid-state file memory devices such as magnetic bubble memory devices and charge-coupled devices have appeared, and some have even been put into practical use. Since this solid-state file memory element does not involve mechanical rotation, it has many advantages over conventional file memory, but in terms of economy,
It is hard to say that it is necessarily advantageous at this point. Therefore, in order to improve economic efficiency, current devices use elements that have partially defective parts to increase the yield of the devices and reduce the overall cost of the device. Hereinafter, a conventional defective loop selection control method and its problems will be described using a magnetic bubble memory device as an example. Figure 1 shows a memory unit consisting of eight magnetic bubble chips, where 1 is a minor loop group that stores and transfers information, and 2 is a major loop that transfers bubbles for reading or writing information. , 3 is a detector for reading information, and 4 is a generator for storing information.

When a rotating magnetic field is applied to the chip, the information of the minor loop 1 and the major loop 2 performs synchronous rotation in the direction of the arrow in the figure. For example, when information at point A in the figure is read out, the information at point A moves on minor loop 1, transfers to major loop 2, then moves on major loop 2, and is read out by detector 3. The transition from the minor loop 1 to the major loop 2 is always performed for a plurality of pieces of information at the same position in each minor loop, and each piece of information is read out serially by the detector 3 in the order of the minor loop position. Multiple chips also rotate synchronously, and information at the same location on each chip is read out at the same timing. For write operations, the basic operations are the same except that the flow of data is the opposite of that for read and the write timing is slightly different from the read timing, so the following explanation will be entirely based on read operations. Now, at present, as mentioned above, magnetic bubble chips are often used with some defective parts still included.

If this defective part becomes a major loop, the chip cannot be used, but if it becomes a minor loop, only the corresponding minor loop becomes defective, and other minor loops and major loops can be used. Therefore, a preliminary minor loop is prepared in advance when creating the chip. Here, 132 minor loops are prepared in one chip, of which 128X. will be actually used, and four will be used as backup loops. FIG. 4 shows the normal and defective states of the minor loops of each chip, with ROJ marks indicating normal loops and 1x marks indicating defective loops. From FIG. 4, all of the minor loop number #0 of each chip is a normal loop, so all the information read at the same timing is valid, and this is set as the 0th byte. Minoru. Looking at step number #1, NO. Since chip No. 2 has a defective loop, NO. In chip No. 2, this information is assigned to the minor loop with minor loop number #2.
Therefore, as shown by the broken line in FIG. O'-
NO. l, NO. 3~NO. The minor loop number of the chip No. 7 is #1 and NO. 2 chip minor loop number #2
constitutes the first byte. In this way, conventionally, information for a defective loop is assigned to a normal minor loop at the next timing within the same chip.

The hardware configuration in this case is shown in FIG. 21, and the control method is shown in FIGS. 5 and 6. In Figure 2, 111 (1 = 0 to 7)
is a magnetic bubble chip NOjll 2 is a read-only memory (ROM) that stores information indicating whether it is a normal loop or a defective loop for each minor loop, 131 is a magnetic bubble chip (4-bit shift that adjusts the timing of information from NO. Register, 141 is shift register 1
31 is a selector for selecting a bit when used from 4 bits, and 15 is a control signal generation circuit that controls the progress of each shift register 131 and the selection function of the selector 141. The data shown in FIG. 5 is stored in the ROM12. The ROM bit positions in FIG. 5 correspond to the chip numbers in FIG. 4, and the addresses in the ROM correspond to the minor loop numbers in FIG. 4, with 0 indicating a normal loop and 1 indicating a defective loop. Now, in one period of the rotating magnetic field applied from the outside, one bit of information is read out from each chip 110 to 117 and stored in the shift registers 130 to 137.

Therefore, first, 4 bits of chip (NO.i) 111, that is, information of minor loop numbers #0, #1, .

FIG. 6a shows whether the information in the shift registers 130 to 137 is valid or invalid at this point. Here, ROJ indicates a valid bit read from a normal loop, and 1×YO indicates an invalid bit read from a defective loop. The contents of ROM12 begin to be read out at the same timing as above. ROMl
The contents read from 2 are expanded by the control signal generation circuit 15, but the contents of the initial ROM address are all 0, and at this time, all shift registers 130 to 1
The third bit of No. 37 is selected by the selectors 140 to 147, and is selected by the external device as the 0th byte information. At the next timing, the shift register 1 increments by 1 bit and becomes the contents shown in FIG. 6b. At this timing, the ROM
From l2, the contents of address 1 in the ROM (27 to 7 = 0,
0, 0, 0, 0, 1, 0, 0) is read out. This indicates that the minor loop of the magnetic bubble chip (NO. 2) 112 is a defective loop, and is expanded by the control signal generation circuit 15 and selected by the selectors 1401141143 to 1401141143.
At 147, the third bit of the corresponding shift register is selected by the selector 14. Then the second bit is selected. Similarly, the read information from the defective loop is skipped by the selector 14 based on the contents of the ROM12, and the read information from the normal loop is sequentially assigned. As described above, in the conventional method, when there is a defective loop, the timing at which each bit constituting the unit information (8 bits in 1 byte in this case) is read from the magnetic bubble chip is different, so the number of bits equal to the number of spare minor loops is The problem was that the amount of hardware required was enormous, such as the need to provide a shift register.

Furthermore, in the conventional method, chips in which the number of defective loops is greater than the number of spare loops cannot be used, which causes a decrease in yield. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method which eliminates the above-mentioned drawbacks of the prior art, which is easy to configure with a small amount of metal materials, and which greatly relaxes restrictions on chip usage and improves chip yield.

To achieve the above object, the present invention provides a memory device consisting of a plurality of information loops such as a magnetic bubble memory or a shift register-like memory such as a CCD, in which memory chips are provided in a number greater than the number of unit information bits, and each chip is It is characterized by having means for reading or writing the same loop information at the same timing, and an additional memory such as a read-only memory for storing whether the loop is a normal loop or a defective loop, and the normal loop is selected based on the information in the additional memory. It is something. Furthermore, if the number of normal loops read and written at the same timing is less than the number of unit information bits, it is determined that the information is defective based on the contents of the additional memory, the information read at that timing is considered unused, and the information to be written is is characterized by a temporary waiting list. Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 7 shows an example of the use of the memory chip according to the present invention and the normal and defective states of the minor loop of each chip.

Here, as in the previous conventional example, the unit information is 8 bits 1
In the conventional example, the number of magnetic bubble chips was 8 chips corresponding to the number of unit information bits, but in the embodiment of the present invention, 10 chips are used. In other words, information is read or written from 10 chips at the same timing, but of the 10 bits corresponding to the 10 chips, 8 bits of the normal loop are used, and if the normal loop is less than 8 bits, the corresponding 10 bits are used. Don't use all the bits. This situation will be explained using FIG. 7. In FIG. 7, all of the 10 chips with minor loop number #0 of each chip are normal loops, and in this case, magnetic bubble chip No. O-corps, the minor loop up to 0th
Part-time job.

For those with minor loop number #1, magnetic bubble chip No. Since the minor loop of No. 2 is defective, the magnetic bubble chip No. 2 is defective. . ~NO. The minor loop of 1, NOU to NOJ3 is the first byte. Minor loop number #2
As for the case of minor loop number #0, magnetic bubble chip NC). 0-NO. A minor loop up to 7 is used as the second byte. For the one with minor loop number #3, magnetic bubble chip No. 5~N
The minor loop of O67 is defective, leaving only seven normal loops. Therefore, all the minor loops at this timing are not used. And the minor loop number #
Magnetic bubble chip No. 4 obtained in 4. O-NO2, NO
The 8 bits from 5 to NO3 are the third byte. The specific hardware structure and control method of the present invention are shown in FIG. 3 and FIG. 8.

In the following explanation, only the read operation will be described to simplify the explanation, but there is no major difference in the write/read operation except that the direction of data is reversed. In Figure 3,
211 (1=0-9) is the magnetic bubble chip No. il2
2 is a read-only memory (ROM) that indicates whether each minor loop that is read and written at the same timing is a normal loop or a defective loop, and stores information indicating that a group of minor loops is a group of defective loops; A selector 24 is used to select a magnetic bubble chip having a normal loop.
A control signal generating circuit 25 generates a selection signal 1 and a signal specifying a group of defective loops, and 25 is a defective byte display signal 7 specifying the group of defective loops. The output information line of the chip (NO.i) 211 is input to the selector 23i. The data shown in Fig. 8 is stored in the ROM 22, and the address in the ROM corresponds to the minor loop number shown in Fig. 7, but unlike the conventional system, the ROM bit position 9 corresponds to the chip number shown in Fig. 7. It is not compatible with , and can be used as follows. If there is no defective loop among 10 minor loops with the same minor loop number, 2
7 to 7 are all 1. When there is one defective loop, the defective chip number is indicated by λ to f, and 27 to 7 are all 1s. When there are two defective loops, the respective defective chip numbers are indicated as 27-27 and 23-7. If there are 3 or more defective loops, set 27 to 7 to 11101110
indicates that it is a bad byte. Now, a rotating magnetic field is applied to each chip, and 10 of minor loop number #0
Assume that a bit is read from each magnetic bubble chip 210-219.

In this case, at the same time, the ROM address 0 is sent from the ROM22.
information is read out. The information at this time is all 1 indicating that the loop is normal, and each selector 231 opens the upper gate 2310 of the 3-input select gates from the control signal generation circuit 24, and the NO. O-NO. The information up to No. 7 magnetic bubble chip 210217 is assumed to be the 0th byte. Next, minor loop number #1 is read out.

In this case, the information at address 1 in the ROM is read from the ROM 22, and ? ~7 is the defective chip number NO. 0010, 27 to 7 indicating 2 are all 1 indicating that there are no more defects.
300, 23101 selectors 232 to 237 select middle gates 2321 to 2371 of the three input gates, and select NO. O, NO. l, NO. 3~NO. The information on the magnetic bubble chips 220, 221, 223 to -226 of No. 8 is assumed to be the first byte. Regarding the next minor loop number #2, as in the case of minor loop number #0, NO. O-
NO. The information on the magnetic bubble chips 210 to 217 of No. 7 is assumed to be the second byte. In the case of the next minor loop number #3, it is in the ROM. The information 11101110 indicating that 27 to 7 are bad bytes from address 3 is read out, and the control signal generation circuit 24 closes all the gates of each selector 231 and sends out the bad byte display signal 25 to the outside at the corresponding timing. Show the signal is disabled! Ru. and,
The 8-bit information consisting of the minor loop number #4 read at the next timing is assumed to be the third byte. The same applies below. As described above, according to the present invention, not only is there no timing shift between the bits constituting one byte as in the conventional method, but also a shift register is no longer required, making it possible to significantly reduce hardware costs.

Furthermore, in the conventional method, a chip containing more than a predetermined number of defective minor loops in one chip could not be used at all.
If the method of the present invention is used, for example, even if 10 chips with 5 defective minor loops are used to constitute one byte, 99.86% of the chips can be used. This effect more than compensates for the increase in the number of chips by 2 chips, and overall economic efficiency is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a memory unit section of a magnetic bubble memory device, FIG. 2 is a block diagram showing a conventional control method for a magnetic bubble memory device, and FIG. 3 is a block diagram showing an embodiment of a control method according to the present invention. Figure 4 is a conceptual diagram showing a conventional method for selecting a defective loop in a magnetic bubble memory device, Figure 5 is a diagram showing the contents of a ROM used in the method for selecting a defective loop in Figure 4, and Figure 6 is a diagram showing a conventional method for selecting a defective loop in a magnetic bubble memory device. FIG. 7 is a conceptual diagram showing the method for selecting a defective loop in a magnetic bubble memory device when the present invention is applied. FIG. 8 is a diagram showing the contents of the shift register when the loop selection method is applied. FIG. 2 is a diagram showing the contents of a ROM used in the defective loop selection method of the present invention. 210-219...Magnetic bubble chip, 22...
...Read-only memory, 230-237...Selector, 24...Control signal generation circuit, 25...
- Bad byte display signal.

Claims (1)

[Claims] 1 Having a plurality of memory areas each containing a plurality of unit storage areas each storing unit information, specifying one unit storage area for each of these memory areas, and storing specific unit information for the specified unit storage area group. In a memory control device that controls transfer of a group of information, an additional memory is provided with a number of memory areas greater than the specific number and stores information indicating the position of an unusable unit storage area within the plurality of memory areas. Memory control characterized in that an area is provided, and the specific number of usable unit storage areas is selected from a group of corresponding unit storage areas in the plurality of memory areas based on information in the additional memory area. method.