JPS605040B2 - pattern processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for extracting or processing a predetermined pattern from two-dimensional pattern data.

A conventional processing procedure for this type of pattern processing will be explained with reference to FIG. Here, as shown in FIG. 1A, when a small area noise of logic 1" or logic 0" is superimposed on the binarized original pattern, a procedure for removing this noise pattern will be described. First, the scanning mask d shown in FIG. 1B is scanned over the original pattern shown in FIG. 1A. That is, each pixel data a, b, c, d, e, f, g, . A logical product operation is performed between h and i, and the result of this operation is used as the pixel data of i. When the mask d is sequentially scanned over the entire pattern by performing this 3 x 3 bit logical product operation, the logic "1" part is enlarged, and the logic "0" part is reduced, as shown in Figure 1B. By being
The black noise 0'' in the white pattern, 1'' is removed.

Next, the scanning mask 3 of FIG. 1C is sequentially scanned over the entire screen with respect to the pattern of FIG. 1B. That is, 3
The logical sum between pixels adjacent to the ×3 bit square is determined as pixel data for i. By the above processing, the first
As shown in figure C, the logic 1" part is vertically reduced and becomes logic -0".
The area is enlarged and returns to the size of the pattern in FIG. 1A. However, in the process described above, the white noise (1'') in the black pattern (0'') still remains. It is necessary to apply a scanning mask 8 to the image, and then apply a scanning mask Q.This invention was made to solve these drawbacks, and the extraction and removal of many types of specific patterns can be done in one step. The object of the present invention is to provide a pattern processing device that can perform high-speed processing.An embodiment of the processing device according to the present invention shown in FIG. 2 will be described below.FIG. 3 shows the main parts of FIG. 2 in detail. In Figure 2, 2
01 is a 3-line shift register that stores 3 lines of pixel data of the original pattern input in synchronization with the transfer clock and sequentially shifts it, and surrounding pixel data of pixel i stored in this register 1, m, n, p, q
, s are the scanning mask/g turns a, b, c, d in FIG.
, e, f, g, and h, respectively. 202 is mask pattern data a, b, c, d, for matching with 8-bit peripheral pixel data j, k, 1, m, n, p, q, s adjacent to pixel data j to be processed;
A matching pattern register 203 sets peripheral pixel data i, k, 1, m'n'p, q, s of the 3-line shift register 201 and matching pattern register 202 for setting e, f, g, h. The mask pattern data a, b, c, d, e, f, g, h, set in advance in
a correlation circuit that compares a correlation degree) with an externally set correlation degree threshold value and outputs the comparison result as a binary logic output;
4 is the output of the correlation circuit 203 and the pixel data i of the original pattern
This is a determination circuit that performs logical operations such as logical sum and logical product and determines which one to extract.

FIG. 3 shows the correlation circuit 203 and determination circuit 204 in FIG.
This figure shows the detailed configuration of . In FIG. 3, 301 is peripheral pixel data j, k, 1 of pixel data i of the original pattern.
, m, n'P'q's, and the matching mask pattern data a, b, c, d, e, f, g, h, respectively, for each corresponding pixel, and if they match, the logical , 1'' signal, and 302 is a correlation degree extraction circuit that counts the number of matching signals for each pixel of the verification circuit 301 and outputs the counted value, that is, the correlation degree of the 8-bit peripheral pattern. A circuit 303 compares the correlation degree output count value of the correlation degree extraction circuit 302 and the set correlation degree threshold value N in terms of magnitude, smallness, and equality, and outputs a binary logical output according to the comparison result. The comparison circuits 304 and 305 are the comparison circuit 303
An AND circuit and an OR circuit 306 are A
This is a selection circuit that selects the output of either the ND circuit 304 or the OR circuit 305 and outputs it.

Next, the operation will be explained.

It is now assumed that the pixel data of the original pattern is sequentially input to the 3-line shift register 201 and sequentially shifted in synchronization with the pixel data transfer clock.

At this time, peripheral pixel data i, k, 1, m'n' of pixel data i forming a 3 x 3 bit square grid shown in FIG. p, q, s are transferred from the 3-line shift register 201 every clock, and matching mask/g turn data a, b, c, d, e, f, g, h,
A matching circuit 301 performs a logical product for each pixel. That is, only the pixel data at the position to be compared is extracted by masking. The output of this matching circuit 301 is masking data of peripheral pixel data of the original pattern. The correlation degree extraction circuit 302 calculates the number of items masked and extracted from peripheral pixel data of pixel data i (i.e., logic "1").
'') and output the counted value as the degree of correlation.
A comparator circuit 303 compares this degree of correlation with a dark correlation value set in advance according to the pattern to be extracted, and if the dark value is greater than, smaller than, or equal to the dark value, a logical value is determined. 1" is specified by MODEI. The output after this comparison (peripheral distribution status data of pixel i) and the pixel data i are ANDed and ORed, and one of the outputs is sent to the selection circuit 306. This is selected and output as new processed pixel data i.The above operations are performed for the entire original pattern, that is, all input pixel data.In this way, the matching mask pattern data, correlation degree threshold, By setting or specifying MODE1 (comparison output select) and MODE2 (calculation mode select) according to the desired pattern, it is possible to extract or remove a predetermined pattern from the original pattern. Figure 4 shows a case in which this is used for noise processing.

Now, the matching mask pattern data a, b, c, d, e,
As f, g, h = (0, 1, 0, 1, 0, 1, 0, 1), pixel data (b, d, f
, h), and count the number of logics, , 1'' of this pixel.

Let this count value (correlation degree) be M. Let the correlation degree threshold be N,
If M>N, the logic output of the comparison circuit 303 t=1'',
If MmiN, MODEI so that t= ,,0''
Specify. Regarding the logical output t and pixel data i determined by the upper, lower, left, and right peripheral distribution conditions of this pixel data i, when pixel data i = 0'', the logical sum of t and i, and when i = 1'', Circuit 306 that determines the logical product of t and i
(in this case, the logic of i is used to specify MODE2) and is adopted as the logic data of the new processed pixel data i. When the above processing is applied to the pattern shown in FIG. 4A, black noise in the white pattern and white noise in the black pattern are removed in one process (FIG. 4B). As described above, by providing the matching mask pattern with a directional mask extraction function and extracting the degree of correlation, the surrounding distribution situation of each pixel can be grasped, and from this, the correct logical value that each pixel should take can be determined. , it is possible to process a pattern rich in arbitrary spatial aptitude in one process. In FIG. 4, noise processing (which is also surface extraction) has been described, but functions such as line segment or curve extraction can also be realized by appropriately selecting each parameter to be set. Therefore, the two-dimensional pattern processing section shown in FIG. 2 can be inserted into the image processing computer as an operator. The above has described processing of a 3 x 3 bit area, but it goes without saying that similar pattern processing can be applied to an M x M (M is an integer) area.
It is also possible to detect curved surfaces and end points. As described above, according to the pattern processing device according to the present invention, the peripheral distribution situation of each pixel position is obtained using an arbitrarily set matching mask pattern and correlation degree, and this data and the data of each pixel are used in a logical operation. , since we are determining the logical value of the true pixel data,
This has the effect of allowing a predetermined pattern to be extracted or removed from the original pattern in one process and at high speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram explaining the procedure of a conventional pattern processing method, FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention, and FIG.
This figure is a circuit configuration diagram showing the main part of FIG. 2, and FIG. 4 is an operation explanatory diagram for explaining the operations of FIGS. 2 and 3. In the figure, 201 is a 3-line data shift register, 202 is a matching pattern register, 203 is a correlation circuit, 204 is a judgment circuit, 301 is a matching circuit, 302 is a correlation degree extraction circuit,
303 is a comparison circuit, 304 is an AND circuit, and 305 is an OR circuit.
Circuit 306 is a selection circuit. In the figures, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Claims] 1. In a device that processes pattern data in which binarized pixels are two-dimensionally arranged, peripheral pixel data of the pixel to be processed and data values are set in advance in correspondence with the peripheral pixels. A matching section that matches the matched matching mask pattern data for each corresponding pixel and outputs matching signals according to the matching results, and counts the number of matching signals of this matching section and outputs the counted value (degree of correlation). a correlation counting unit; a comparison unit that compares the count value of the correlation counting unit with a preset correlation degree threshold and outputs a logic signal according to the comparison result;
A pattern processing device comprising: a calculation unit that performs a logical operation on the logic signal of the comparison unit and the pixel data to be processed in a predetermined mode, and outputs the output of the calculation as processed pixel data. 2. The pattern processing device according to claim 1, wherein the logical operation mode of the arithmetic unit is designated (selected) according to the data value of the pixel data to be processed.