JPS605105B2 - solid-state imaging device - Google Patents
solid-state imaging deviceInfo
- Publication number
- JPS605105B2 JPS605105B2 JP51107795A JP10779576A JPS605105B2 JP S605105 B2 JPS605105 B2 JP S605105B2 JP 51107795 A JP51107795 A JP 51107795A JP 10779576 A JP10779576 A JP 10779576A JP S605105 B2 JPS605105 B2 JP S605105B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- solid
- imaging device
- state imaging
- impurity layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
本明は同一半導体単結晶基板上に製作した感光素子と感
光素子からの出力を時間順次的に選択読み出しをするた
めのスイッチおよび走査回路とから構成される固体撮像
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a solid-state imaging device comprising a photosensitive element manufactured on the same semiconductor single crystal substrate, and a switch and a scanning circuit for selectively reading out the output from the photosensitive element in time-sequential manner. It is related to.
固体撮像装置は現行のテレビジョン放送で使用されてい
る撮像用電管並みの解像力を備える必要があり、このた
め500×50の固の光電変換素子およびそれに相当し
た(x,y)座標選択用のスイッチ、またスイッチを開
閉する500段づつのx走査回路およびy走査回路が必
要となる。したがって、通常は集積密度の高いシリコン
MOS集積回路技術を用いて作られる。第1図に光導電
性物質を感光素子とする従来の撮像素子の断面構造を示
す。A solid-state imaging device must have a resolution comparable to that of the imaging tube used in current television broadcasting, and for this reason, a 500 x 50 solid photoelectric conversion element and an equivalent (x, y) coordinate selection device are required. switches, and 500 stages of x-scan and y-scan circuits to open and close the switches. Therefore, they are typically made using silicon MOS integrated circuit technology, which has a high integration density. FIG. 1 shows a cross-sectional structure of a conventional image sensor using a photoconductive substance as a photosensitive element.
ここで1は第一導電型(たとえばn型)の半導体基板、
2はスイッチ用MOS電界効果トランジスタ(以下MO
STと略す)である。3は酸化膜4を介して設けたゲー
ト電極、また5および6は第二導電型(たとえばp型)
の高濃度不純物層で、以下5をドレィン、6をソースと
称する。Here, 1 is a semiconductor substrate of the first conductivity type (for example, n-type),
2 is a MOS field effect transistor for switching (hereinafter referred to as MO
(abbreviated as ST). 3 is a gate electrode provided through an oxide film 4, and 5 and 6 are second conductivity type (for example, p type)
5 is hereinafter referred to as a drain and 6 as a source.
7はドレィン5と抵抗性接触のとれた平面電極、8は光
導電性薄膜、9ははターゲット電圧10を印加する透明
電極である。7 is a planar electrode in resistive contact with the drain 5, 8 is a photoconductive thin film, and 9 is a transparent electrode to which a target voltage 10 is applied.
本素子の動作を簡単に説明する。光導電性薄膜8は入射
光に応じてその導電率が変化し、その結果、平面電極7
には入射光に相当した電圧△Vがターゲット電圧より供
給される。走査回路の出力する選択パルスによりスイッ
チ部2が導適すると電極7すなわちドレィン5に現れた
電圧△Vがソース6より映像信号として読み出される。
ところで光導電性薄膜はしきし、値電圧があり、通常2
0〜30Vである。The operation of this device will be briefly explained. The photoconductive thin film 8 changes its conductivity depending on the incident light, so that the planar electrode 7
A voltage ΔV corresponding to the incident light is supplied from the target voltage. When the switch unit 2 is turned on by the selection pulse output from the scanning circuit, the voltage ΔV appearing at the electrode 7, that is, the drain 5, is read out from the source 6 as a video signal.
By the way, photoconductive thin films have a high voltage value, usually 2.
It is 0-30V.
したがって、薄膜にはしきい値電圧以上の電圧を印加す
る必要があり、一般に80べ150Vの電圧が印加され
る。変化した電圧△Vは入射光量が多くなるに従って、
ターゲット電圧VTとしきい値電圧Vthの差に近づく
あるいは等しくなり、例えばVTを100V、Vthを
30Vとすれば△Vは70 Vになり、本電圧がドレィ
ン5に現われる。一方通常のMOSプロセスで製作でき
るMOST破壊電圧は20V、高々30Vであるから光
量が多い場合はドレィン接合部で電圧破壊が起こり、光
信号を取り出すことができなくなる。また変化電圧△V
は光量に一次比例して増加するため、電圧破壊の防止の
点から電圧△Vを小さく抑えようとすると、入射光量の
上限を抑える必要があり、検出可能な光量範囲を狭める
ことになる。本発明の目的は上記した固体撮像装置にお
いて高電圧のかかるドレィン接合部の破壊電圧を向上さ
せることである。以下本発明を実施例によって詳細に説
明する。Therefore, it is necessary to apply a voltage higher than the threshold voltage to the thin film, and generally a voltage of 80V to 150V is applied. The changed voltage △V increases as the amount of incident light increases.
The target voltage VT approaches or becomes equal to the difference between the target voltage VT and the threshold voltage Vth. For example, if VT is 100 V and Vth is 30 V, ΔV becomes 70 V, and this voltage appears at the drain 5. On the other hand, the breakdown voltage of a MOST that can be manufactured using a normal MOS process is 20V, or at most 30V, so when the amount of light is large, voltage breakdown occurs at the drain junction, making it impossible to extract optical signals. Also, the changing voltage △V
increases in linear proportion to the amount of light, so if we try to keep the voltage ΔV low from the viewpoint of preventing voltage breakdown, it is necessary to suppress the upper limit of the amount of incident light, which narrows the range of the amount of light that can be detected. An object of the present invention is to improve the breakdown voltage of the drain junction to which high voltage is applied in the solid-state imaging device described above. The present invention will be explained in detail below using examples.
第2図に本発明の固体撮像素子を構成する感光素子の断
面構造を示す。11はn型半導体基板、1 2はスイッ
チ用MOST部である。FIG. 2 shows a cross-sectional structure of a photosensitive element constituting the solid-state image sensor of the present invention. Reference numeral 11 represents an n-type semiconductor substrate, and reference numeral 12 represents a switch MOST section.
1 3は酸化膜14を介して設けたゲート電極、また1
5,16は高濃度のP型不純物層で形成したソースおよ
びドレインである。1 3 is a gate electrode provided through an oxide film 14;
Reference numerals 5 and 16 denote sources and drains formed of highly concentrated P-type impurity layers.
17はドレインの平面および深さ方向を囲んで形成した
抵濃度のP型不純物層である。Reference numeral 17 denotes a resistive P-type impurity layer formed to surround the drain in the plane and depth direction.
18はドレィン16と抵抗性鞍触のとれた平面電極であ
り、19は光導電性薄膜、20はターゲット電圧21を
印加するための透明電極である。18 is a planar electrode in contact with the drain 16, 19 is a photoconductive thin film, and 20 is a transparent electrode for applying a target voltage 21.
一般にPN(あるいはNP)接合の破壊電圧は、接合近
傍のP領域において印加電圧によって生じる空乏層の幅
の和に比例すると考えてよく、従って、不純物濃度が小
さくなるにつれ破壊電圧は増加する。上記低濃度のP型
不純物層17の濃度は基板と同程度あるいはそれ以下で
もよく、必要な耐圧に応じて1び4〜1ぴ6(/地)に
選ぶのが良い。また低濃度のP型不純物層の深さはMO
STのチャネル長より小さくする必要があり、例えば、
チャネル長がloAm、高濃度不純物層の深さが1仏m
のときは、2〜5仏m程度に選ぶのが良い。In general, the breakdown voltage of a PN (or NP) junction can be considered to be proportional to the sum of the widths of depletion layers generated by applied voltages in the P region near the junction, and therefore, the breakdown voltage increases as the impurity concentration decreases. The concentration of the low concentration P-type impurity layer 17 may be the same as or lower than that of the substrate, and is preferably selected from 1 to 4 to 1 to 6 (/ground) depending on the required breakdown voltage. Also, the depth of the low concentration P-type impurity layer is MO
It needs to be smaller than the channel length of ST, for example,
The channel length is loAm, and the depth of the high concentration impurity layer is 1 French m.
In this case, it is best to choose between 2 and 5 meters.
不純物濃度は1び4〜1ぴ6/城程度が好ましい。これ
により、破壊電圧を1び6個/洲の濃度で約60V、ま
た1ぴ1個/洲の濃度で約150Vに高めることができ
る。したがって、動作電圧および信頼度が高くなるばか
りでなく、入射光量の上限も従来素子の場合より、4〜
6倍広げることができ、入射光コントラストの大きい種
々の用途に使用することが可能になる。以上の製造方法
は、従来の製造工程にP拡散工程を追加するだけでよく
、しかも、糠像素子の集積密度を犠牲にすることなく容
易に実現できる。The impurity concentration is preferably about 1 to 1 to 1 to 6. As a result, the breakdown voltage can be increased to about 60 V at a concentration of 1 to 6 particles/plane, and to about 150 V at a concentration of 1 particle/plane. Therefore, not only is the operating voltage and reliability higher, but the upper limit of the amount of incident light is 4 to 4.
It can be expanded by 6 times, making it possible to use it for various applications where the contrast of incident light is large. The above manufacturing method only requires adding a P diffusion step to the conventional manufacturing process, and can be easily realized without sacrificing the integration density of the bran image elements.
次に、他の実施例について説明する。第3図にオフセッ
ト・ゲート構造のMOSTをもつ撮像素子の断面構造を
示す。22はn型半導体基板、23はスイッチ用MOS
T部である。Next, other embodiments will be described. FIG. 3 shows a cross-sectional structure of an image sensor having an offset gate structure MOST. 22 is an n-type semiconductor substrate, 23 is a switch MOS
This is the T section.
24は酸化膜25を介して設けたゲート電極、また26
,27は高濃度のP型不純物層で形成したソースおよび
ドレィンである。24 is a gate electrode provided through an oxide film 25, and 26
, 27 are sources and drains formed of highly concentrated P-type impurity layers.
28はドレィン27の一部に接触しゲート電極24の左
端まで伸びた低濃度のP型不純物層である。28 is a low concentration P-type impurity layer that contacts a part of the drain 27 and extends to the left end of the gate electrode 24.
29はドレィン27と抵抗性接触のとれた平面電極であ
り、3川ま光導電性薄膜、31はターゲット電圧32を
印加するための透明電極である。29 is a planar electrode in resistive contact with the drain 27; three electrodes are photoconductive thin films; 31 is a transparent electrode for applying a target voltage 32;
この構造においては抵抗性の拡散層2Mこよる電圧降下
のために、拡散層28の右端部と基板22間にかかる電
圧が小さくなり、その結果電圧破壊が起りにくくなる。
しかし、拡散層28のもつ抵抗が必要以上に大きくなる
と、コンダクタンスが小さくなるため、一般に拡散層2
8の形成には、イオン打込みを利用して不純物層の長さ
を5〃m、濃度を1×1び1/嫌程度のとき、破壊電圧
200Vを得るこ.とができる。(打込み深さは通常l
Am程度で、この時不純物層の不純物密度は1び5/が
程度である。)本素子を製造するためには、従来の製造
工程に低濃度のP型不純物層を形成する工程を追加する
だけでよく、破壊電圧の高い撮像素子を得ることができ
る。したがって、素子の動作電圧余裕および検出光量の
範囲を広め、かつ信頼度を高めることができ、本発明の
実用上の効果は非常に大きい。なお上記の実施例では感
光素子とつながったスイッチとして、MOSTを用いて
説明したが、本発明の趣旨を逸脱しない範囲で接合型電
界効果トランジスタ、バイポーラ型トランジスタを用い
て構成できることは勿論である。In this structure, due to the voltage drop caused by the resistive diffusion layer 2M, the voltage applied between the right end of the diffusion layer 28 and the substrate 22 is reduced, and as a result, voltage breakdown is less likely to occur.
However, if the resistance of the diffusion layer 28 becomes larger than necessary, the conductance decreases, so generally the diffusion layer 28
8 was formed by using ion implantation to obtain a breakdown voltage of 200 V when the length of the impurity layer was 5 m and the concentration was about 1 × 1 and 1/2. I can do that. (The driving depth is usually l.
At this time, the impurity density of the impurity layer is about 1 to 5/. ) In order to manufacture this device, it is only necessary to add a step of forming a low concentration P-type impurity layer to the conventional manufacturing process, and an image sensor with high breakdown voltage can be obtained. Therefore, it is possible to widen the operating voltage margin of the element and the range of the amount of detected light, and to improve the reliability, and the practical effects of the present invention are very large. In the above embodiment, a MOST was used as the switch connected to the photosensitive element, but it is of course possible to use a junction field effect transistor or a bipolar transistor without departing from the spirit of the present invention.
第1図は従来の固体撮像素子の断面図であり、第2図は
本発明による固体撮像素子の断面図、第3図は本発明に
よる第2図とは異なる固体撮像素子の断面図である。
努1図
弟Z図
繁3図FIG. 1 is a cross-sectional view of a conventional solid-state image sensor, FIG. 2 is a cross-sectional view of a solid-state image sensor according to the present invention, and FIG. 3 is a cross-sectional view of a solid-state image sensor different from FIG. 2 according to the present invention. . Tsutomu 1 illustration Younger brother Z illustration Shigeru 3 illustration
Claims (1)
るスイツチ用MOS電界効果トランジスタを備えた電極
パターンを2次元状に配列し、前記電極上に光導電性膜
を設けた固体撮像素子において、前記スイツチ用MOS
電界効果トランジスタの前記電極パターンに抵抗性接触
した第2導電型高濃度不純物層を低濃度の第二導電型不
純物層で囲んだことを特徴とする固体撮像装置。1. In a solid-state imaging device, in which an electrode pattern including MOS field effect transistors for switches that are opened and closed by a scanning circuit is arranged on a first conductivity type semiconductor substrate in a two-dimensional manner, and a photoconductive film is provided on the electrode, MOS for switch
A solid-state imaging device characterized in that a second conductivity type high concentration impurity layer in resistive contact with the electrode pattern of a field effect transistor is surrounded by a second conductivity type impurity layer having a low concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51107795A JPS605105B2 (en) | 1976-09-10 | 1976-09-10 | solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51107795A JPS605105B2 (en) | 1976-09-10 | 1976-09-10 | solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5333524A JPS5333524A (en) | 1978-03-29 |
| JPS605105B2 true JPS605105B2 (en) | 1985-02-08 |
Family
ID=14468214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51107795A Expired JPS605105B2 (en) | 1976-09-10 | 1976-09-10 | solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605105B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54147790A (en) * | 1978-05-12 | 1979-11-19 | Victor Co Of Japan Ltd | Solidstate pick up element |
| JPS5689176A (en) * | 1979-12-20 | 1981-07-20 | Matsushita Electric Ind Co Ltd | Solid image pickup device |
| JPS59139672A (en) * | 1984-01-20 | 1984-08-10 | Hitachi Ltd | Solid-state image pickup element |
-
1976
- 1976-09-10 JP JP51107795A patent/JPS605105B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5333524A (en) | 1978-03-29 |
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