JPS6051133B2 - natural logarithm converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a natural logarithm conversion device that can easily perform natural logarithm conversion of data representing various physical quantities using a pipeline method.

There are many systems that require natural logarithmic transformation of measured physical quantity data, including calculation processing of X-ray absorption coefficients in computerized X-ray tomography devices.

For example, in the above device, the intensity of the incident X-ray is 10, the intensity of the X-ray transmitted through the object is 11, the X-ray absorption coefficient of the object is μ, and the X-ray transmission length of the object is X.

When this is transformed into natural logarithms, it is shown as
By measuring the intensity ratio (IO/1) and the distance X, the X-ray absorption coefficient μ can be determined very easily. . However, with the above-mentioned device that is currently in practical use, 512 pieces of data are obtained per direction, and this is calculated for each of the 60 spinning directions to obtain 3072ω pieces of data, and the X-ray absorption coefficient μ of each part is calculated as a matrix. These images are used to construct diagnostic images. Therefore, it is necessary to perform natural logarithmic transformation on all of this data, and it is essential to speed up the natural logarithmic transformation processing. Devices that perform such natural logarithm conversion processing have been proposed and put into practical use, such as those that use series expansion and those that perform table search, but the former has the disadvantage of poor processing accuracy and long calculation time. The latter has the disadvantage that the memory capacity becomes extremely large depending on the input data length. The present invention was made in view of these circumstances.
The purpose of this is to normalize the data, perform a table search, and perform correction processing to make it possible to easily and accurately obtain natural logarithm-transformed data, and also to introduce the Vibrine calculation. It is an object of the present invention to provide a natural logarithm conversion device having a simple and highly practical configuration that can substantially shorten the time required for conversion processing.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 schematically shows the form of natural logarithm conversion processing performed by this device, in which the first step A1 normalizes the input data 4. It consists of a second step B that performs a first-order approximation calculation, and a third step C that corrects the data obtained by the first-order approximation calculation using the normalization information and obtains natural logarithm-transformed data '0gx.4. Ru.

These first to third steps A, B, and C are sequentially executed in a vibratory manner. Now, assume that the input data X is provided as 16-bit digital data consisting of the upper 8 bits K1 and the lower 8 bits W1, as shown in FIG. 2, for example.

In this case, data x can be expressed as X=K1.multidot.7+W1, and is set in input register 1 of the device whose schematic configuration is shown in FIG.

Shift number tables 2 and 8 containing this input register 1
The bit shifter 3 constitutes a normalization circuit that executes the first step A. In the normalization process, when the data has "0" in the upper bits, such as "0010", this is bit-shifted toward the upper bits to create normalized data "1000", and the number of shifts is Table 2 defines the number of bit shifts. That is, the shift number table 2 is composed of, for example, a ROM having a gate capacity of 256 words and 4 bits, and receives the upper 8 bit data K1 of the input data X as an address and outputs the bit shift number. In response to this bit shift number, the 8-bit shifter 3 bit-shifts the data X1, performs data conversion so that [1] is placed in the most significant bit, and normalizes the data. Therefore, the data normalized through this 8-bit shifter 3? is indicated as.

The first-order approximation calculation circuit B that performs the process of the second step B is R
It consists of a natural logarithm conversion table 4 made up of OM, a first correction table 5, a multiplier 6, an adder 7, and a second correction table 8 made of ROM.

The natural logarithm table 4 and the first correction table 5 input the upper 8-bit data K2 of the normalized data formula as an address and output pre-registered table information, that is, primary approximation data and correction data. This correction data and the lower 8 bit data W2 of the normalized data X2
is multiplied by a multiplier 6, and first-order approximation data is added to this multiplication output data by an adder 7 to obtain the normalized data ? Data FOgX2 that has been subjected to natural logarithm transformation is obtained. That is, the normalized data? Considering the natural logarithmic transformation of

If we focus on the third term on the right side of the above equation, we get K2.23ku JW2.
Since a relationship is established that is sufficiently larger than , it is possible to approximately express the above equation as follows. ．． 1 (″<)6tυ ~ −0 thin 1 ~ (ko
-Of these, 8e
Since 0g2 is given as a constant, the remaining 2
Input data to calculate terms! It would be a good idea to do this for .

However, since the data K2 is 8-bit data at most, the converted data is registered in advance at each address using a 256-word ROM, and the data K2 is input into the address, and the converted data EOgK2 and 17/K2 are input. Find each of them. By the way, 8'0g2 and 1/2
Since both 8 are constants, by reading data including these, we can obtain (8e0g2+'0gK2) and 17/K
2 and 7 can be found at the same time. Therefore, multiplier 6
Multiply the above 1/K2・7 by W2, and add (
By adding the data of 8f0g2+EOgK2) in the adder 7, the natural logarithm transformed data FOgX2 can be easily obtained. The second correction table 8 is made up of a 9-word ROM, and stores an amount of natural logarithm conversion data corresponding to the bit shift number n.
That is, the normalized data j has a relationship where n is the number of bit shifts, and is expressed as follows.

Therefore, this NfOg2 is obtained in accordance with the bit shift number n, and in the third step C, the following calculation is performed by the adder 9, and the mutually corrected natural logarithm conversion data EOgxl is obtained.

Tables 1 to 3 below show the address structure of the memories forming each of the tables 2, 4, 5, and 8.

In this way, shift number table 2 will be 256 words 4
Tables 4 and 5 can be realized using a ROM of 256 words and (16+8) bits, and the second correction table 8 can be realized using a ROM of 9 words and 16 bits. can be simplified.

As explained above, according to the present device, the first to third steps A, B, and C are successively executed in a vibrating manner to perform natural logarithmic transformation on input data X extremely easily and with high precision. It can be done.

Moreover, the memory capacity can be kept small by performing normalization processing, which simplifies the system configuration. It can be simplified. Furthermore, by the above-mentioned vibe line calculation, when the conversion process for a certain data X1 is being performed in the third step, the calculation for the next data Since the calculation can be executed on the next data X3), the time required for calculation processing can be substantially reduced. Therefore, it is extremely effective when natural logarithm transformation is performed on a huge amount of physical data as described above. Note that the present invention is not limited to the above embodiments.

For example, the maximum number of bit shifts for input data, the bit length of data to be processed, etc. may be determined according to specifications. It goes without saying that the memory structure of the table may be determined in accordance with this specification. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, in which FIG. 1 is a diagram showing an outline of processing steps, FIG. 2 is a diagram showing a format of input data, and FIG. 3 is a schematic diagram of the overall configuration of the apparatus. 1...Input register, 2...Shift number table, 3...8-bit sister, 4...
Natural logarithm table, 5...first correction table,
6... Multiplier, 7... Adder, 8...
...Second correction table, 9...Adder.

Claims (1)

[Scope of Claims] 1. An input register for storing N-bit input digital data, and inputting data of the upper few bits of the input digital data to predetermine the number n of bit shifts necessary for normalizing the input digital data. a shift number table read from a registered table; a shifter that shifts and normalizes the input digital data stored in the input register by n bits according to the bit shift number n read from the shift number table; a conversion circuit for obtaining first natural logarithm data for n-bit shifted and normalized digital data; and means for obtaining second natural logarithm data (nlog2) corresponding to the bit shift number n;
A natural logarithm conversion device comprising: an adder that subtracts the second natural logarithm data from the first natural logarithm data to obtain natural logarithm conversion data of the input digital data. 2. The conversion circuit divides the normalized N-bit digital data into k-bit upper bit group data K and (N-k) bit lower-order bit group data W, and converts the normalized N-bit digital data into natural logarithm data for the upper bit group data K. In addition to finding logK, constant (N-k)lOg2 and variable W/K・2^
(＾N＾−＾K＾) respectively and add these respective data to obtain first natural logarithm data for the normalized N-bit digital data. natural logarithm transformer.