JPS6051135B2 - Instruction word verification method by adding parity bits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction word verification method by adding a parity bit.

Almost all of today's general-purpose computers are based on so-called stored program processors, in which programs are stored in a storage device and are sequentially executed one by one by an arithmetic processor controller. It executes instructions, and the instruction words have multiple word lengths, and the word code is interpreted differently depending on the order of each word.

However, in a processing device as described above, which has a program stored in a storage device and has instruction words of multiple word lengths in which control is performed within the program, the program number is 1, , -, j-.
1゛,,,,,,fuyu''・Yu^ Police, Le A2l
−ゝ,ヲ５ L 書 し い Ｇａｎ 4 to 41 The operand (which is the data or information item used in the operation) and the operand (for example, according to the instruction code of addition or multiplication)
If a command is misunderstood, there is a risk that the program will run out of control.

Therefore, in order to improve reliability, it is generally desirable to be able to check whether the fetched item is an instruction or an operand. For this purpose, two methods are typically considered. The first method is to add one bit as information to distinguish between an instruction and an operand, and the second method is to use some bits in one word to create an operand code to identify the operand. It is.

However, the first method requires redundant bits on the data bus and its interface.

In the second method, if a check is performed using a microprogram or hardware at the time of instruction fetch or operand fetch, it takes time for the processing or requires a check circuit. Since a bit that specifies a certain thing is required, the amount of information as an operand is reduced, and it also has drawbacks such as being impractical for general-purpose microcomputers, etc., where the instruction or operand code is determined. On the other hand, conventionally, in order to improve the reliability of words used in computers, one bit called a parity bit is added to the code of the word itself, and errors are detected by a parity check.

Using this, for example, even parity for instructions,
By setting odd parity for Oberand,
A method of checking instructions and operands has been considered, but this method has the disadvantage of not being able to detect errors in the order of fetching operands due to program counter errors when the operands are composed of multiple words. It was hot. In view of these points, in the present invention, each instruction and each operand of the instruction word are used in a stored program type processing device that has an instruction word with a plurality of word lengths and the word code is interpreted differently depending on the order of the words in the instruction word. For each predetermined number of unit bits, the odd-even parity for distinguishing each is applied so that the combination of parity bits differs depending on the order of the instruction or each operand, and when fetching an instruction or each operand, each parity bit is The instruction and each operand are verified by the combination of You can also test instructions and operands.

Next, we will explain one embodiment of the method of the present invention.In the case of an instruction word of 16 bits per word, first, the 16 bits are divided into an upper byte and a lower byte of 8 bits each, and then the instruction and operand are separated. Parity bits are added to each byte and lower byte to specify odd-even parity, and instructions 1 and operands 1 to 3 are added as shown in the table below.
A maximum of four combinations are possible. In the table, U. P (UpperParity) is the parity for the upper byte, L. P (Lower Parity)
indicates parity for the lower bite.

In the case of one embodiment based on Table 1, the instruction with the parity bit added and the contents of the operand words are shown in the first example.
It is a diagram.

A is the upper byte, B is the lower byte, and C and D are parity bits added to the parts A and B, respectively.

Therefore, if the instruction words of a program stored in a storage device are to be executed in the order of instruction, operand 1, instruction, instruction, operand 1, operand 2, the monitor side first specifies even-even when decoding starts. The first instruction, then the even/odd operand 1, then the even/even second instruction, the even/even third instruction, the even/odd operand 1, and the odd/even operand 2 are sequentially fetched from the storage device to the control device. Instructions and operands are checked for each word to confirm that they are correct, and errors are corrected before the instruction is executed.

Figure 2 is a block diagram of one embodiment of the instruction and operand verification circuit used in this case, in which 16 bits per word are divided into upper and lower 8 bits, and a parity bit is added to each upper and lower byte. According to the parity bit of each word or a combination thereof, parity testing circuits 1a and 1b are used to test whether the parity is even or odd, respectively, and the first AND circuits 2a and 2
b, 2c, and 2d to obtain instructions with four combinations of even-even, even-odd, odd-even, and odd-odd, and odd-even outputs of operand 1, operand 2, and operand 3.

On the other hand, an instruction interpretation/execution circuit 3 is provided, and a command (non-command) fetch signal, that is, (
operand 1) + (operand 2) ten (operand 3)
, operand 1 (not operand 1) fetch signal, i.e. (instruction) + (operand 2) + (operand 3),
Operand 2 (not operand 2) Fetch signal, that is (instruction) + (operand 1) + (operand 3), 7
operand 3 (not operand 3) i.e. (instruction) + (
The respective outputs of operand 1) + (operand 2) are taken out, and the above-mentioned instructions, operand 1, operand 2, and operand 3 are processed by the second AND circuits 4a, 4b, 4c, and 4d.
A check is performed and a signal is taken out by checking the odd-even parity output of the circuit, and errors are corrected by this.The above verification circuit can verify instructions and operands of up to 4 word length. This makes it possible to easily verify instructions and operands to prevent program malfunctions and runaways.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the contents of one embodiment of an instruction word, and FIG. 2 is a block diagram of an instruction operand verification circuit. A is the upper byte, B is the lower byte, C and D are additional parity.
Bits 1a and 1b are parity verification circuits, 2a to 2d are first AND circuits, 3 is an instruction interpretation and execution circuit, 4a to 4d
is the second AND circuit.

Claims (1)

[Claims] 1. In a stored program processing device that has an instruction word with a plurality of word lengths, and the word code is interpreted differently depending on the order of the words in the instruction word, the respective distinctions are odd-even parity,
A parity bit characterized in that different combinations of parity bits are added depending on the order of the instruction and each operand, and the instruction and each operand are tested by the combination of respective parity bits when fetching the instruction or each operand. Verification method for imperative words by addition.